SMSC Computer Drive USB3310 User Manual

USB3310  
Hi-Speed USB Transceiver  
with 1.8V ULPI Interface -  
Multi-Frequency Reference  
Clock  
Data Brief  
PRODUCT FEATURES  
USB-IF “Hi-Speed” compliant to the Universal Serial  
Bus Specification Rev 2.0  
Integrated ESD protection circuits  
Up to ±15kV without any external devices  
Carkit UART mode for non-USB serial data transfers  
Industrial Operating Temperature -40°C to +85°C  
Packaging Options  
Interface compliant with the ULPI Specification  
revision 1.1 as a Single Data Rate (SDR) PHY  
1.8V IO Voltage (±10%)  
TM  
24 pin QFN lead-free RoHS compliant package  
flexPWR Technology  
(4 x 4 x 0.90 mm height)  
Low current design ideal for battery powered  
applications  
Applications  
“Sleep” mode tri-states all ULPI pins and places the  
part in a low current state  
The USB3310 is targeted for any application where a Hi-  
Speed USB connection is desired and when board  
space, power, and interface pins must be minimized.  
Supports FS pre-amble for FS hubs with a LS device  
attached (UTMI+ Level 3)  
Supports HS SOF and LS keep-alive pulse  
The USB3310 is well suited for:  
Includes full support for the optional On-The-Go  
(OTG) protocol detailed in the On-The-Go  
Supplement Revision 1.0a specification  
Cell Phones  
PDAs  
Supports the OTG Host Negotiation Protocol (HNP)  
and Session Request Protocol (SRP)  
MP3 Players  
GPS Personal Navigation  
Scanners  
Allows host to turn VBUS off to conserve battery  
power in OTG applications  
External Hard Drives  
Digital Still and Video Cameras  
Portable Media Players  
Entertainment Devices  
Printers  
Support OTG monitoring of VBUS levels with internal  
comparators  
“Wrapper-less” design for optimal timing performance  
and design ease  
Low Latency Hi-Speed Receiver (43 Hi-Speed clocks  
Max) allows use of legacy UTMI Links with a ULPI  
bridge  
Set Top Boxes  
Video Record/Playback Systems  
IP and Video Phones  
Gaming Consoles  
POS Terminals  
Internal 5V cable short-circuit protection of ID, DP  
and DM lines to VBUS or ground  
13, 19.2, 24 or 26MHz Selectable Reference  
ClockFrequency  
0 to 3.6V input drive tolerant  
Able to accept “noisy” clock sources  
Internal low jitter PLL for 480MHz Hi-Speed USB  
operation  
Internal detection of the value of resistance to ground  
on the ID pin  
Integrated battery to 3.3V LDO regulator  
2.2uF bypass capacitor  
100mV dropout voltage  
SMSC USB3310 REV C  
PRODUCT PREVIEW  
Revision 1.11 (10-31-08)  
 
Hi-Speed USB Transceiver with 1.8V ULPI Interface - Multi-Frequency Reference Clock  
General Description  
The USB3310 is a highly integrated Hi-Speed USB 2.0 Transceiver (PHY) that supports systems  
architectures based on a 13, 19.2, 24 or 26MHz reference clock. The frequency of the reference clock  
is selected by configuration. It is designed to be used in both commercial and industrial temperature  
applications.  
The USB3310 meets all of the electrical requirements to be used as a Hi-Speed USB Host, Device,  
or an On-the-Go (OTG) device. In addition to the supporting USB signaling the USB3310 also provides  
USB UART mode.  
USB3310 uses the industry standard UTMI+ Low Pin Interface (ULPI) to connect the USB PHY to the  
Link. The industry standard ULPI interface uses a method of in-band signaling and status byte transfers  
between the Link and PHY, to facilitate a USB session. By using in-band signaling and status byte  
transfers the ULPI interface requires only 12 pins.  
The USB3310 uses SMSC’s “wrapper-less” technology to implement the ULPI interface. This “wrapper-  
less” technology allows the PHY to achieve a low latency transmit and receive time. SMSC’s low  
latency transceiver allows an existing UTMI Link to be reused by adding a UTMI to ULPI bridge. By  
adding a bridge to the ASIC the existing and proven UTMI Link IP can be reused.  
REFSEL[1] REFSEL[0]  
REFCLK  
Low Jitter  
Integrated  
PLL  
RBIAS  
BIAS  
VBUS  
ID  
OTG  
RESETB  
VBAT  
VDD33  
VDD18  
Integrated  
Power  
Management  
Hi-Speed  
USB  
Transceiver  
DP  
ULPI  
DM  
Registers  
and State  
Machine  
STP  
NXT  
DIR  
ULPI Interface  
CLKOUT  
Carkit  
DATA[7:0]  
Figure 1 USB3310 Block Diagram  
The USB3310 is designed to operate with an external reference clock at one of four frequencies. By  
using an available reference, the USB3310 saves the cost of a crystal reference.  
The USB3310 includes a integrated 3.3V LDO regulator to generate its own supply from power applied  
at the VBAT pin. The voltage on the VBAT pin can range from 3.1 to 5.5V. The regulator dropout  
voltage is less than 100mV which allows the PHY to continue USB signaling when the voltage on  
VBAT drops to 3.1V. The USB transceiver will continue to operate at lower voltages, although some  
parameters may be outside the limits of the USB specifications. If the user would like to provide a 3.3V  
supply to the USB3310, the VBAT and VDD33 pins should be connected together.  
The USB3310 also includes integrated pull-up resistors that can be used for detecting the attachment  
of a USB Charger. By sensing the attachment to a USB Charger, a product using the USB3310 can  
charge its battery at more than the 500mA allowed when charging from a USB Host.  
SMSC USB3310 REV C  
3
Revision 1.11 (10-31-08)  
PRODUCT PREVIEW  
 
Hi-Speed USB Transceiver with 1.8V ULPI Interface - Multi-Frequency Reference Clock  
USB3310 Pin Locations and Descriptions  
Package Diagram with Pin Locations  
The pinout below is viewed from the top of the package.  
ID  
VBUS  
VBAT  
VDD3.3  
DM  
1
2
3
4
5
6
18  
17  
16  
15  
14  
13  
NXT  
DATA0  
DATA1  
24Pin QFN  
4x4mm  
REFSEL[0]  
REFSEL[1]  
DATA2  
DP  
Figure 2 USB3310 QFN Pinout - Top View  
Pin Definitions  
The following table details the pin definitions for the figure above.  
Table 1 USB3310 Pin Description  
DIRECTION/ ACTIVE  
PIN  
BALL  
NAME  
ID  
TYPE  
LEVEL  
DESCRIPTION  
Input,  
Analog  
N/A  
ID pin of the USB cable. For non-OTG  
applications this pin can be floated. For  
an A-Device ID is grounded. For a B-  
Device ID is floated.  
1
B1  
I/O,  
N/A  
N/A  
VBUS pin of the USB cable. This pin is  
used for the Vbus comparator inputs and  
for Vbus pulsing during session request  
protocol.  
2
C1  
VBUS  
VBAT  
Analog  
Power  
Regulator input. The regulator supply can  
be from 5.5V to 3.1V.  
3
C2  
Revision 1.11 (10-31-08)  
4
SMSC USB3310 REV C  
PRODUCT PREVIEW  
 
Hi-Speed USB Transceiver with 1.8V ULPI Interface - Multi-Frequency Reference Clock  
Table 1 USB3310 Pin Description (continued)  
PIN  
BALL  
DIRECTION/ ACTIVE  
NAME  
TYPE  
LEVEL  
DESCRIPTION  
Power  
N/A  
3.3V Regulator Output. A 2.2uF (<1 ohm  
ESR) bypass capacitor to ground is  
required for regulator stability. The  
bypass capacitor should be placed as  
close as possible to the USB3310.  
4
D2  
VDD3.3  
I/O,  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
D- pin of the USB cable.  
5
D1  
DM  
Analog  
I/O,  
Analog  
D+ pin of the USB cable.  
6
E1  
DP  
I/O,  
CMOS  
7
E2  
DATA[7]  
DATA[6]  
DATA[5  
DATA[4]  
CLKOUT  
ULPI bi-directional data bus. DATA[7] is  
the MSB.  
I/O,  
CMOS  
8
E3  
ULPI bi-directional data bus.  
ULPI bi-directional data bus.  
ULPI bi-directional data bus.  
I/O,  
CMOS  
9
D3  
I/O,  
CMOS  
10  
E4  
Output,  
CMOS  
60MHz reference clock output. All ULPI  
signals are driven synchronous to the  
rising edge of this clock.  
11  
E5  
I/O,  
N/A  
N/A  
N/A  
N/A  
12  
D5  
DATA[3]  
DATA[2]  
ULPI bi-directional data bus.  
CMOS  
I/O,  
CMOS  
13  
D4  
ULPI bi-directional data bus.  
Input,  
CMOS  
These signals select one of the available  
reference frequencies:  
[1] [0] Description  
14  
C4  
REFSEL[1]  
REFSEL[0]  
0
0
1
1
0
1
0
1
13MHz  
19.2MHz  
26MHz  
24MHz  
Input,  
CMOS  
15  
B4  
I/O,  
N/A  
N/A  
16  
C5  
DATA[1]  
DATA[0]  
NXT  
ULPI bi-directional data bus.  
CMOS  
I/O,  
CMOS  
17  
B5  
ULPI bi-directional data bus. DATA[0] is  
the LSB.  
Output,  
CMOS  
High  
The PHY asserts NXT to throttle the data.  
When the Link is sending data to the  
PHY, NXT indicates when the current  
byte has been accepted by the PHY. The  
Link places the next byte on the data bus  
in the following clock cycle.  
18  
A5  
SMSC USB3310 REV C  
5
Revision 1.11 (10-31-08)  
PRODUCT PREVIEW  
 
Hi-Speed USB Transceiver with 1.8V ULPI Interface - Multi-Frequency Reference Clock  
Table 1 USB3310 Pin Description (continued)  
DIRECTION/ ACTIVE  
PIN  
BALL  
NAME  
DIR  
TYPE  
LEVEL  
DESCRIPTION  
Output,  
CMOS  
N/A  
Controls the direction of the data bus.  
When the PHY has data to transfer to the  
Link, it drives DIR high to take ownership  
of the bus. When the PHY has no data to  
transfer it drives DIR low and monitors  
the bus for commands from the Link.  
19  
A4  
Input,  
CMOS  
High  
The Link asserts STP for one clock cycle  
to stop the data stream currently on the  
bus. If the Link is sending data to the  
PHY, STP indicates the last byte of data  
was on the bus in the previous cycle.  
20  
A3  
STP  
Power  
N/A  
N/A  
External 1.8V Supply input pin. This pad  
needs to be bypassed with a 0.1uF  
capacitor to ground, placed as close as  
possible to the USB3310.  
21  
B3  
VDD1.8  
Input,  
CMOS,  
When low, the part is suspended with all  
of the I/O tri-stated. When high the  
USB3310 will operate as a normal ULPI  
device.  
22  
B2  
RESETB  
Input,  
N/A  
N/A  
N/A  
Reference Clock input.The required  
frequency is configured by the  
REFSEL[1:0] pins.  
23  
A2  
REFCLK  
RBIAS  
GND  
CMOS  
Analog,  
CMOS  
Rbias pin. This pin requires an 8.06k  
(±1%) resistor to ground, placed as close  
as possible to the USB3310.  
24  
A1  
Ground  
Ground.  
FLAG  
C3  
QFN only: The flag should be connected  
to the ground plane with a via array  
under the exposed flag. This is the main  
ground for the IC.  
Revision 1.11 (10-31-08)  
6
SMSC USB3310 REV C  
PRODUCT PREVIEW  
 
Hi-Speed USB Transceiver with 1.8V ULPI Interface - Multi-Frequency Reference Clock  
Application Diagrams  
Steady state voltage at the VBUS pin must not be  
allowed to exceed VVMAX  
.
Link Controller  
USB331X  
RVBUS may be installed in this configuration to  
assist in protecting the VBUS pin. 820 Ohms  
will protect against VBUS transients up to  
8.5V. 10K Ohms will protect against  
7
8
9
10  
12  
13  
16  
17  
20  
18  
19  
11  
22  
23  
DATA7  
DATA6  
DATA5  
DATA4  
DATA3  
DATA2  
DATA1  
DATA0  
STP  
DATA7  
DATA6  
DATA5  
DATA4  
DATA3  
DATA2  
DATA1  
DATA0  
STP  
transients up to 10V.  
RVBUS  
2
VBUS  
3.1-5.5V  
Supply  
NXT  
NXT  
DIR  
DIR  
The capacitor CVBUS must be  
CLKOUT  
CLKOUT  
RESETB  
Reference  
3
VBAT  
installed on this side of RVBUS  
.
RESETB  
CBYP  
REFCLK  
Signal at REFCLK  
must comply with  
V and V  
4
VDD3.3  
USB  
Receptacle  
CVBUS  
COUT  
Pin Strap  
IH  
IL  
1
Determines  
REFCLK  
frequency  
VBUS  
14  
15  
REFSEL[1]  
REFSEL[0]  
5
6
2
DM  
DM  
DP  
3
DP  
1.8V Supply  
NC  
21  
24  
1
VDD18  
RBIAS  
SHIELD  
GND  
ID  
CBYP  
CDC_BLOCK  
8.06k  
GND FLAG  
Figure 3 USB3310 QFN Application Diagram (Device)  
SMSC USB3310 REV C  
7
Revision 1.11 (10-31-08)  
PRODUCT PREVIEW  
 
Hi-Speed USB Transceiver with 1.8V ULPI Interface - Multi-Frequency Reference Clock  
Voltage at the VBUS pin must not be allowed  
Link Controller  
to exceed VVMAX  
.
CPEN  
RVBUS may be installed in this  
configuration to assist in protecting  
the VBUS pin. 820 Ohms will  
protect against VBUS transients up  
to 8.5V.  
USB331X  
7
8
9
DATA7  
DATA6  
DATA5  
DATA4  
DATA3  
DATA2  
DATA1  
DATA0  
STP  
DATA7  
DATA6  
DATA5  
DATA4  
DATA3  
DATA2  
DATA1  
DATA0  
STP  
VBUS Switch  
10  
12  
13  
16  
17  
20  
18  
19  
11  
22  
23  
RVBUS  
2
3
EN  
IN  
VBUS  
OUT  
5V  
NXT  
DIR  
NXT  
3.1 - 5.5V  
Supply  
DIR  
CLKOUT  
RESETB  
REFCLK  
CLKOUT  
RESETB  
Reference  
The capacitor CVBUS must be  
installed on this side of R  
VBAT  
.
VBUS  
CBYP  
Signal at REFCLK  
must comply with  
V and V  
4
USB  
VDD3.3  
Receptacle  
Pin Strap  
IH  
IL  
COUT  
CVBUS  
1
2
3
4
Determines  
REFCLK  
frequency  
VBUS  
DM  
14  
15  
REFSEL[1]  
REFSEL[0]  
5
6
1
DM  
DP  
ID  
DP  
1.8V Supply  
ID  
21  
24  
VDD18  
RBIAS  
CBYP  
GND  
SHIELD  
8.06k  
GND FLAG  
Figure 4 USB3310 QFN Application Diagram (Host or OTG)  
Revision 1.11 (10-31-08)  
8
SMSC USB3310 REV C  
PRODUCT PREVIEW  
 
Package Outline  
Figure 5 24-Pin QFN, 4x4mm Body, 0.5mm Pitch  
 

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