SMSC Home Theater Server COM20020 User Manual

COM20020  
COM20020 ULANC  
Universal Local Area Network Controller  
with 2K x 8 On-Board RAM  
FEATURES  
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24-Pin Embedded Network Controller/  
Transceiver/RAM  
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Data Rates from 2.5 Mbps to 156.25 Kbps  
24-Pin DIP or 28-Pin PLCC Package  
Flexible Media Interface:  
Ideal for Industrial/Factory Automation  
and Automotive Applications  
Deterministic, 2.5 Mbps, Token Passing  
ARCNET Protocol  
Minimal Microcontroller and Media  
Interface Logic Required  
Flexible Microcontroller Interface for Use  
with 80XX, 68XX, etc.  
Automatically Detects Type of  
Microcontroller Interface:  
-
-
-
Traditional Hybrid Interface for Long  
Distances  
RS485 Differential Driver Interface for  
Low Cost, Low Power, High Reliability  
Backplane Mode for Direct Connection to  
Media in Short Distance Applications  
·
Eight, 256-Byte Pages Allow 4 Pages TX  
and RX Plus Scratch-Pad Memory  
No Wait-State Arbitration  
Programmable TXEN Polarity  
Next ID Readable  
Internal Clock Prescaler for Slower Network  
Speed without Slowing Arbitration  
Operating Temperature Range of -40oC to  
+85oC, or 0oC to +70oC  
Self-Reconfiguration Protocol  
Supports up to 255 Nodes  
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·
-
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Non-Multiplexed or Multiplexed Bus  
Separate nRD & nWR Lines or DIR &  
nDS Lines  
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Full 2Kx8 On-Chip RAM  
Command Chaining for Top Performance  
Reduced Reconfiguration Times  
Sequential Access to Internal RAM  
Software Programmable Node ID  
Duplicate Node ID Detection  
Powerful Diagnostics  
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·
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Supports Various Network Topologies (Star,  
Tree, Bus...)  
CMOS, Single +5V Supply  
·
Receive All Mode  
GENERAL DESCRIPTION  
SMSC's COM20020 is a member of the family  
of Industrial Network Controllers from Standard  
Microsystems Corporation. The device is a  
special purpose communications controller for  
networking microcontrollers and intelligent  
peripherals in industrial, automotive, and  
embedded control environments using an  
ARCNET® protocol engine. The small 24-pin  
package, flexible microcontroller and media  
interfaces, eight-page message support, and  
extended temperature range of the COM20020  
make  
it  
the  
only  
true  
network  
 
controller optimized for use in industrial and  
automotive applications. Using an ARCNET  
protocol engine is the ideal solution for factory  
automation applications because it provides a  
token-passing protocol, a highly reliable and  
proven networking scheme, and a data rate of  
up to 2.5 Mbps when using the COM20020.  
network. The deterministic nature of ARCNET  
is essential in mission critical applications.  
The integration of the 2Kx8 RAM buffer on-chip,  
the Command Chaining feature, the 2.5 Mbps  
maximum data rate, and the internal diagnostics  
make the COM20020 the highest performance  
industrial communications device available.  
With  
microcontroller,  
only  
one  
a
COM20020  
complete communications  
and  
one  
A token-passing protocol provides predictable  
response times because each network event  
occurs within a predetermined time interval,  
based upon the number of nodes on the  
node may be implemented.  
ARCNET is a registered trademark of Datapoint Corporation  
PIN CONFIGURATION  
VDD  
24  
A0/nMUX  
1
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
nRD/nDS  
nWR/DIR  
nCS  
2
3
4
5
6
A1  
A2/ALE  
AD0  
25 24 23 22 21 20 19  
nWR/DIR  
nPULSE 1  
XTAL2  
18  
17  
26  
27  
nRD/nDS  
VDD  
nINTR  
AD1  
XTAL1  
28  
1
16  
15  
nRESET IN  
nTXEN  
AD2  
D3  
VDD  
VSS  
7
8
A0/nMUX  
A1  
RXIN  
D4  
14  
13  
12  
2
3
4
nPULSE2  
D5  
9
10  
11  
12  
N/C  
D7  
A2/ALE  
AD0  
nPULSE1  
XTAL2  
D6  
D7  
5
6
7
8
9
10 11  
VSS  
XTAL1  
Packages: 24-Pin DIP or 28-Pin PLCC  
Ordering Information:  
COM20020  
P
PACKAGE TYPE: P = Plastic, LJP = PLCC  
TEMP RANGE: (Blank) = Commercial: 0°C to +70°C  
I = Industrial: -40°C to +85°C  
DEVICE TYPE: 20020 = Universal Local Area Network Controller  
(with 2K x 8 RAM)  
3
 
DESCRIPTION OF PIN FUNCTIONS  
DIP PIN PLCC PIN  
NO. NO.  
NAME  
MICROCONTROLLER INTERFACE  
SYMBOL  
DESCRIPTION  
1-3  
1-3  
Address  
0-2  
A0/nMUX,  
A1,A2/ALE  
Input. On a non-multiplexed bus, these  
signals are directly connected to the low bits  
of the host address bus. On a multiplexed  
address/data bus, A0/nMUX is tied low, A1  
is left open, and A2 is tied to the Address  
Latch Enable signal of the host. A1 is  
connected to an internal pull-up resistor.  
4-11  
4-6,8-12  
Data 0-7  
AD0-AD2,  
D3-D7  
Input/Output. On a non-multiplexed bus,  
these signals are used as the data lines for  
the device. On a multiplexed address/data  
bus, AD0-AD2 act as the address lines  
(latched by ALE) and as the low data lines  
for the device. D3-D7 are always used for  
data only. These signals are connected to  
internal pull-up resistors.  
23  
27  
nRead/nData nRD/nDS  
nStrobe  
Input. On a 68XX-like bus, this active low  
signal is issued by the microcontroller as the  
data strobe signal to strobe the data onto  
the bus. On a 80XX-like bus, this active low  
signal is issued by the microcontroller to  
indicate a read operation. In this case, a  
logic "0" on this pin, when the COM20020 is  
accessed, enables data from the device to  
the data bus to be read by the  
microcontroller.  
22  
26  
nWrite/  
Direction  
nWR/DIR  
Input. On a 68XX-like bus, this signal is  
issued by the microcontroller as the  
Read/nWrite signal to determine the  
direction of data transfer. In this case, a  
logic "1" selects a read operation, while a  
logic "0" selects a write operation. In this  
case, data is actually strobed by the nDS  
signal. On an 80XX-like bus, this active low  
signal is issued by the microcontroller to  
indicate a write operation. In this case, a  
logic "0" on this pin, when the COM20020 is  
accessed, enables data from the data bus to  
be written to the device.  
4
 
DIP PIN PLCC PIN  
NO. NO.  
NAME  
SYMBOL  
DESCRIPTION  
19  
23  
nReset in  
nRESET IN Input. This active low signal issued by the  
microcontroller executes a hardware reset.  
It is used to activate the internal reset  
circuitry within the COM20020.  
20  
24  
nInterrupt  
nINTR  
Output. This active low signal is generated  
by the COM20020 when an enabled  
interrupt condition occurs. nINTR returns to  
its inactive state when the interrupt status  
condition or the corresponding interrupt  
mask bit is reset.  
21  
25  
nChip Select nCS  
Input. This active low signal issued by the  
microcontroller selects the COM20020 for  
an access.  
TRANSMISSION MEDIA INTERFACE  
16,15  
19,18  
nPulse 2,  
nPulse 1  
nPULSE2,  
nPULSE1  
Output. In Normal Mode, these active low  
signals carry the transmit data information,  
encoded in pulse format, from the  
COM20020 to the media driver circuitry.  
When the device is in Backplane Mode, the  
nPULSE1 signal driver is programmable  
(push/pull or open-drain), while the  
nPULSE2 signal provides a clock with  
frequency of crystal/4.  
nPULSE1 is  
connected to a weak internal pull-up resistor  
in backplane mode.  
17  
18  
20  
21  
Receive In  
RXIN  
Input. This signal carries the receive data  
information from the line receiver circuitry to  
the COM20020.  
nTransmit  
nEnable  
nTXEN  
Output. This signal is used prior to the  
Power-up to enable the line drivers for  
transmission. The polarity of the signal is  
programmable by grounding the nPULSE2  
pin.  
nPULSE2 floating before Power-up: nTXEN  
active low (Default option)  
nPULSE2 grounded before Power-up:  
nTXEN active high (This option is only  
available in Backplane Mode)  
MISCELLANEOUS  
13,14  
16,17  
Crystal  
Oscillator  
XTAL1,  
XTAL2  
An external crystal should be connected to  
these pins. If an external TTL clock is used  
5
 
DIP PIN PLCC PIN  
NO. NO.  
NAME  
SYMBOL  
DESCRIPTION  
instead, it must be connected to XTAL1 with  
a 390W pull-up resistor, and XTAL2 should  
be left floating.  
24  
12  
15,28  
7,14,22  
Power  
Supply  
VDD  
VSS  
+5 Volt Power Supply pin.  
Ground  
Ground pin.  
6
 
Power On  
Reconfigure  
Timer has  
Send  
Reconfigure  
Burst  
Timed Out  
Read Node ID  
Write ID to  
RAM Buffer  
1
Set NID=ID  
N
Y
Start  
Reconfiguration  
Timer (840 mS)  
Invitation  
to Transmit to  
this ID?  
N
Y
Y
N
Free Buffer  
Enquiry to  
this ID?  
TA?  
Y
N
SOH?  
Y
N
Transmit  
NAK  
RI?  
Y
N
RI?  
Transmit  
ACK  
Write SID  
to Buffer  
N
No Activity  
for 82  
Broadcast?  
Y
Transmit  
Free Buffer  
Enquiry  
N
uS?  
Y
DID  
=0?  
No  
Send  
Packet  
Y
Y
Activity  
for 74.7  
us?  
Set NID=ID  
N
N
N
Broadcast  
Enabled?  
Y
N
ACK?  
DID  
=ID?  
Start Timer:  
T=(255-ID)  
x 146 us  
Y
Y
N
Y
Was Packet  
Broadcast?  
N
Set TA  
Y
NAK?  
1
Write Buffer  
with Packet  
N
Activity  
On Line?  
Y
No  
Y
Pass the  
Token  
Activity  
Set TA  
N
for 74.7  
us?  
N
N
N
CRC  
OK?  
N
T=0?  
No  
Increment  
NID  
Y
N
Y
Activity  
Y
N
Y
for 74.7  
ACK?  
Set TMA  
us?  
LENGTH  
OK?  
Y
Y
DID  
=0?  
Set RI  
ID refers to the identification number of the ID assigned to this node.  
-
-
NID refers to the next identification number that receives the token after  
after this ID passes it.  
N
N
DID  
=ID?  
SID refers to the source identification.  
-
-
DID refers to the destination identification.  
Y
SOH refers to the start of header character; preceeds all data packets.  
-
SEND ACK  
FIGURE 1 - COM20020 OPERATION  
7
 
PROTOCOL DESCRIPTION  
following protocol description assumes a 2.5  
NETWORK PROTOCOL  
Mbps data rate. For slower data rates, an  
internal clock divider scales down the clock  
frequency. Thus all timeout values are scaled  
up as shown in the following table:  
Communication on the network is based on a  
token passing protocol. Establishment of the  
network configuration and management of the  
network protocol are handled entirely by the  
COM20020's internal microcoded sequencer. A  
processor or intelligent peripheral transmits data  
TIMEOUT  
DATA RATE  
W/20MHz  
XTAL  
SCALING  
FACTOR  
(MULTIPLY BY)  
CLOCK  
PRESCALER  
by simply loading  
a
data packet and its  
destination ID into the COM20020's internal  
RAM buffer, and issuing a command to enable  
the transmitter. When the COM20020 next  
receives the token, it verifies that the receiving  
node is ready by first transmitting a FREE  
BUFFER ENQUIRY message. If the receiving  
node transmits an ACKnowledge message, the  
data packet is transmitted followed by a 16-bit  
CRC. If the receiving node cannot accept the  
packet (typically its receiver is inhibited), it  
transmits a Negative AcKnowledge message  
and the transmitter passes the token. Once it  
has been established that the receiving node  
can accept the packet and transmission is  
complete, the receiving node verifies the packet.  
If the packet is received successfully, the  
receiving node transmits an ACKnowledge  
message (or nothing if it is not received  
successfully) allowing the transmitter to set the  
appropriate status bits to indicate successful or  
unsuccessful delivery of the packet. An interrupt  
mask permits the COM20020 to generate an  
interrupt to the processor when selected status  
bits become true. Figure 1 is a flow chart  
illustrating the internal operation of the  
COM20020 connected to a 20 MHz crystal  
oscillator.  
2.5 Mbps  
1.25 Mbps  
625 Kbps  
312.5 Kbps  
156.25 Kbps  
1
2
4
8
16  
¸ 8  
¸ 16  
¸ 32  
¸ 64  
¸ 128  
Example: IDLE LINE Timeout @ 2.5 Mbps = 82  
ms. IDLE LINE Timeout for 156.2 Kbps is 82 ms  
* 16 = 1.3 ms  
NETWORK RECONFIGURATION  
A significant advantage of the COM20020 is its  
ability to adapt to changes on the network.  
Whenever  
deactivated,  
a
new node is activated or  
NETWORK  
a
RECONFIGURATION is performed. When a  
new COM20020 is turned on (creating a new  
active node on the network), or if the  
COM20020 has not received an INVITATION  
TO TRANSMIT for 840mS, or if a software reset  
occurs, the COM20020 causes a NETWORK  
RECONFIGURATION  
by  
sending  
a
RECONFIGURE BURST consisting of eight  
marks and one space repeated 765 times. The  
purpose of this burst is to terminate all activity  
on the network. Since this burst is longer than  
any other type of transmission, the burst will  
interfere with the next INVITATION TO  
TRANSMIT, destroy the token and keep any  
other node from assuming control of the line.  
DATA RATES  
The COM20020 is capable of supporting data  
rates from 156.25 Kbps to 2.5 Mbps. The  
8
 
When any COM20020 senses an idle line for  
greater than 82mS, which occurs only when the  
token is lost, each COM20020 starts an internal  
timeout equal to 146ms times the quantity 255  
minus its own ID. The COM20020 starts  
network reconfiguration by sending an invitation  
to transmit first to itself and then to all other  
nodes by decrementing the destination Node ID.  
If the timeout expires with no line activity, the  
COM20020 starts sending INVITATION TO  
TRANSMIT with the Destination ID (DID) equal  
to the currently stored NID. Within a given  
network, only one COM20020 will timeout (the  
one with the highest ID number). After sending  
BROADCAST MESSAGES  
Broadcasting gives a particular node the ability  
to transmit a data packet to all nodes on the  
network simultaneously. ID zero is reserved for  
this feature and no node on the network can be  
assigned ID zero. To broadcast a message, the  
transmitting node's processor simply loads the  
RAM buffer with the data packet and sets the  
DID equal to zero. Figure 8 illustrates the  
position of each byte in the packet with the DID  
residing at address 0X01 or 1 Hex of the  
current page selected in the "Enable Transmit  
from Page fnn" command. Each individual node  
has the ability to ignore broadcast messages by  
setting the most significant bit of the "Enable  
Receive to Page fnn" command (see Table 6) to  
a logic "0".  
the  
INVITATION  
TO  
TRANSMIT,  
the  
COM20020 waits for activity on the line. If there  
is no activity for 74.7mS, the COM20020  
increments the NID value and transmits another  
INVITATION TO TRANSMIT using the NID  
equal to the DID. If activity appears before the  
74.7mS timeout expires, the COM20020 releases  
EXTENDED TIMEOUT FUNCTION  
control of the line.  
RECONFIGURATION,  
During NETWORK  
INVITATIONS TO  
There are three timeouts associated with the  
COM20020 operation. The values of these  
timeouts are controlled by bits 3 and 4 of the  
Configuration Register and bit 5 of the Setup  
Register.  
TRANSMIT are sent to all NIDs (1-255).  
Each COM20020 on the network will finally have  
saved a NID value equal to the ID of the  
COM20020 that it released control to. At this  
point, control is passed directly from one node  
to the next with no wasted INVITATIONS TO  
TRANSMIT being sent to ID's not on the  
Response Time  
The Response Time determines the maximum  
propagation delay allowed between any two  
nodes, and should be chosen to be larger than  
the round trip propagation delay between the  
two furthest nodes on the network plus the  
maximum turn around time (the time it takes a  
network,  
until  
the  
next  
NETWORK  
RECONFIGURATION occurs. When a node is  
powered off, the previous node attempts to pass  
the token to it by issuing an INVITATION TO  
TRANSMIT. Since this node does not respond,  
the previous node times out and transmits  
another INVITATION TO TRANSMIT to an  
incremented ID and eventually a response will  
be received.  
particular COM20020 to start sending  
message in response to a received message)  
a
which is approximately 12.7mS. The round trip  
propagation delay is  
a
function of the  
transmission media and network topology. For  
typical system using RG62 coax in  
a
a
The NETWORK RECONFIGURATION time  
depends on the number of nodes in the network,  
the propagation delay between nodes, and the  
highest ID number on the network, but is  
typically within the range of 24 to 61 ms.  
baseband system, a one way cable propagation  
delay of 31mS translates to a distance of about 4  
miles. The flow chart in Figure 1 uses a value  
of 74.7mS (31 + 31 + 12.7) to determine if any  
node will respond.  
9
 
Unlike asynchronous protocols, there is  
a
Idle Time  
constant amount of time separating each data  
byte. On a 2.5 Mbps network, each byte takes  
exactly 11 clock intervals of 400ns each. As a  
result, one byte is transmitted every 4.4mS and  
the time to transmit a message can be precisely  
determined. The line idles in a spacing (logic  
"0") condition. A logic "0" is defined as no line  
activity and a logic "1" is defined as a negative  
pulse of 200nS duration. A transmission starts  
with an ALERT BURST consisting of 6 unit  
intervals of mark (logic "1"). Eight bit data  
characters are then sent, with each character  
preceded by 2 unit intervals of mark and one  
The Idle Time is associated with a NETWORK  
RECONFIGURATION. Figure 1 illustrates that  
during a NETWORK RECONFIGURATION one  
node will continually transmit INVITATIONS TO  
TRANSMIT until it encounters an active node.  
All other nodes on the network must distinguish  
between this operation and an entirely idle line.  
During  
NETWORK  
RECONFIGURATION,  
activity will appear on the line every 82mS. This  
82mS is equal to the Response Time of 74.7mS  
plus the time it takes the COM20020 to start  
retransmitting another message (usually another  
INVITATION TO TRANSMIT).  
unit interval of space.  
Five types of  
transmission can be performed as described  
below:  
Reconfiguration Time  
Invitations To Transmit  
If any node does not receive the token within the  
Reconfiguration Time, the node will initiate a  
NETWORK RECONFIGURATION. The ET2  
and ET1 bits of the Configuration Register allow  
the network to operate over longer distances  
than the 4 miles stated earlier. The logic levels  
on these bits control the maximum distances  
over which the COM20020 can operate by  
controlling the three timeout values described  
An Invitation To Transmit is used to pass the  
token from one node to another and is sent by  
the following sequence:  
·
·
An ALERT BURST  
An EOT (End Of Transmission: ASCII code  
04H)  
above.  
For proper network operation, all  
·
Two (repeated) DID (Destination  
ID) characters  
COM20020's connected to the same network  
must have the same Response Time, Idle Time,  
and Reconfiguration Time.  
ALERT  
BURST  
EOT  
DID  
DID  
LINE PROTOCOL  
Free Buffer Enquiries  
The ARCNET line protocol is considered  
isochronous because each byte is preceded by a  
start interval and ended with a stop interval.  
A Free Buffer Enquiry is used to ask another  
node if it is able to accept a packet of data. It is  
sent by the following sequence:  
·
·
·
An ALERT BURST  
An ENQ (ENQuiry: ASCII code 85H)  
Two (repeated) DID (Destination ID)  
characters  
ALERT  
BURST  
ENQ  
DID  
DID  
10  
 
Data Packets  
· A single COUNT character which is the 2's  
complement of the number of data bytes to  
follow if a short packet is sent, or 00H  
followed by a COUNT character if a long  
packet is sent  
A Data Packet consists of the actual data being  
sent to another node. It is sent by the following  
sequence:  
· N data bytes where COUNT = 256-N (or 512-  
N for a long packet)  
· An ALERT BURST  
· An SOH (Start Of Header--ASCII code 01H)  
· An SID (Source ID) character  
· Two (repeated) DID (Destination ID)  
characters  
· Two CRC (Cyclic Redundancy Check)  
characters. The CRC polynomial used is:  
X16 + X15 + X2 + 1.  
Acknowledgements  
Negative Acknowledgements  
An Acknowledgement is used to acknowledge  
reception of a packet or as an affirmative  
response to FREE BUFFER ENQUIRIES and is  
sent by the following sequence:  
A Negative Acknowledgement is used as a  
negative  
response  
to  
FREE  
BUFFER  
ENQUIRIES and is sent by the following  
sequence:  
· An ALERT BURST  
· An ACK (ACKnowledgement--ASCII code  
86H) character  
· An ALERT BURST  
· A NAK (Negative Acknowledgement--ASCII  
code 15H) character  
ALERT  
BURST  
ACK  
ALERT  
BURST  
NAK  
11  
 
SYSTEM DESCRIPTION  
will not be changed until hardware  
Refer to Description of Pin  
reset.  
MICROCONTROLLER INTERFACE  
The top halves of Figures 2 and 3 illustrate  
Functions section for details on the related  
signals. All accesses to the internal RAM and  
the internal registers are controlled by the  
COM20020. The internal RAM is accessed via  
a pointer-based scheme (refer to the Sequential  
Access Memory section), and the internal  
registers are accessed via direct addressing.  
Many peripherals are not fast enough to take  
advantage of high-speed microcontrollers. Since  
microcontrollers do not typically have READY  
inputs, standard peripherals cannot extend  
cycles to extend the access time. The access  
time of the COM20020, on the other hand, is so  
fast that it does not need to limit the speed of  
typical  
COM20020  
interfaces  
to  
the  
microcontrollers. The interfaces consist of an 8-  
bit data bus, an address bus, and a control bus.  
In order to support  
a
wide range of  
microcontrollers without requiring glue logic and  
without increasing the number of pins, the  
COM20020 automatically detects and adapts to  
the type of microcontroller being used. Upon  
hardware reset, the COM20020 first determines  
whether the read and write control signals are  
separate READ and WRITE signals (like the  
80XX) or DIRECTION and DATA STROBE (like  
the 68XX). To determine the type of control  
signals, the device requires the software to  
execute at least one write access to external  
memory before attempting to access the  
COM20020. The device defaults to 80XX-like  
signals. Once the type of control signals are  
determined, the COM20020 remains in this  
interface mode until the next hardware reset  
the microcontroller.  
The COM20020 is  
designed to be flexible so that it is independent  
of the microcontroller speed.  
The COM20020 provides for no wait state  
arbitration via direct addressing to its internal  
registers and  
a
pointer based addressing  
occurs.  
The second determination the  
scheme to access its internal RAM. The pointer  
may be used in auto-increment mode for typical  
sequential buffer emptying or loading, or it can  
be taken out of auto-increment mode to perform  
random accesses to the RAM. The data within  
the RAM is accessed through the data register.  
Data being read is prefetched from memory and  
placed into the data register for the  
microcontroller to read. It is important to notice  
that only by writing a new address pointer  
(writing to an address pointer low), one obtains  
the contents of COM20020 internal RAM.  
Performing only read from the Data Register  
does not load new data from the internal RAM.  
During a write operation, the data is stored in  
the data register and then written into memory.  
Whenever the pointer is loaded for reads with a  
new value, data is immediately prefetched to  
prepare for the first read operation.  
COM20020 makes is whether the bus is  
multiplexed or non-multiplexed. To determine  
the type of bus, the device requires the software  
to write to an odd memory location followed by a  
read from an odd location before attempting to  
access the COM20020. The signal on the A0  
pin during the odd location access tells the  
COM20020 the type of bus. Since multiplexed  
operation requires A0 to be active low, activity  
on the A0 line tells the COM20020 that the bus  
is non-multiplexed. The device defaults to  
multiplexed operation. Both determinations may  
be made simultaneously by performing  
a
WRITE followed by a READ operation to an odd  
location within the COM20020 Address space  
20020 registers.  
Once the type of bus is  
determined, the COM20020 remains in this  
interface mode until hardware reset occurs.  
Whenever nCS and nRD are activated, the  
preset determinations are assumed as final and  
12  
 
XTAL1  
XTAL2  
COM20020  
AD0-AD7  
ALE  
AD0-AD2, D3-D7  
A2/BALE  
nCS  
RXIN  
A15  
75176B or  
Equiv.  
RESET  
nRESET IN  
nTXEN  
nPULSE1  
nPULSE2  
nRD/nDS  
nRD  
nWR/DIR  
nINTR  
nWR  
GND  
nINT1  
Differential Driver  
Configuration  
A0/nMUX  
Media Interface  
may be replaced  
*
with Figure A, B or C.  
8051  
27 pF  
27 pF  
FIGURE 2 - MULTIPLEXED, 8051-LIKE BUS INTERFACE WITH RS-485 INTERFACE  
+5V  
2
RXIN  
+5V  
Receiver  
6
RXIN  
HFD3212-002  
7
100 Ohm  
TXEN  
Transmitter  
HFE4211-014  
nPULSE1  
nPULSE2  
GND  
3
nPULSE1  
+5V  
2
6
7
2 Fiber Interface  
(ST Connectors)  
BACKPLANE CONFIGURATION  
NOTE: COM20020 must be in backplane mode  
FIGURE B  
FIGURE A  
13  
 
XTAL1  
COM20020  
XTAL2  
D0-D7  
A0  
D0-D7  
A0/nMUX  
A1  
RXIN  
A1  
A2  
A2/BALE  
nCS  
75176B or  
Equiv.  
A7  
TXEN  
nPULSE1  
nPULSE2  
nRES  
nIOS  
nRESET IN  
GND  
nRD/nDS  
nWR/nDIR  
nINTR  
R/nW  
Differential Driver  
Configuration  
nIRQ1  
* Media Interface  
may be replaced  
with Figure A, B or C.  
XTAL  
1
XTAL  
2
6801  
27 pF  
27 pF  
20MH  
z
XTAL  
FIGURE 3 - NON-MULTIPLEXED, 6801-LIKE BUS INTERFACE WITH RS-485 INTERFACE  
+5V  
HYC9068 or  
10  
uF  
+
0.47  
uF  
HYC9088  
6
RXIN  
RXIN  
12  
11  
N/C  
nTXEN  
0.01 uF  
1KV  
5.6K  
1/2W  
5.6K  
1/2W  
nPULSE1  
nPULSE2  
nPULSE1  
nPULSE2  
GND  
17, 19,  
4, 13, 14  
3
Traditional Hybrid  
Configuration  
0.47  
uF  
-5V  
+
10  
uF  
FIGURE C  
14  
 
TRANSMISSION MEDIA INTERFACE  
reception of data consisting of 1, 1, 0.  
The bottom halves of Figures 2 and 3 illustrate  
the COM20020 interface to the transmission  
media used to connect the node to the network.  
Table 1 lists different types of cable which are  
suitable for ARCNET applications.1 The user  
may interface to the cable of choice in one of  
three ways:  
Backplane Configuration  
The Backplane Open Drain Configuration is  
recommended for cost-sensitive, short-distance  
applications  
like  
backplanes  
and  
instrumentation. This mode is advantageous  
because it saves components, cost, and power.  
Traditional Hybrid Interface  
Since the Backplane Configuration encodes  
data differently than the traditional Hybrid  
Configuration, nodes utilizing the Backplane  
Configuration cannot communicate directly with  
The Traditional Hybrid Interface is that which is  
used with previous ARCNET devices. The  
Hybrid Interface is recommended if the node is  
to be placed in a network with other Hybrid-  
nodes  
utilizing  
the  
Traditional  
Hybrid  
Interfaced nodes.  
The Traditional Hybrid  
Configuration.  
Interface is for use with nodes operating at 2.5  
Mbps only. The transformer coupling of the  
Hybrid offers isolation for the safety of the  
system and offers high Common Mode  
Rejection. The Traditional Hybrid Interface uses  
circuits like SMSC's HYC9068 or HYC9088 to  
transfer the pulse-encoded data between the  
cable and the COM20020. The COM20020  
transmits a logic "1" by generating two 100nS  
non-overlapping negative pulses, nPULSE1 and  
nPULSE2. Lack of pulses indicates a logic "0".  
The nPULSE1 and nPULSE2 signals are sent to  
the Hybrid, which creates a 200nS dipulse  
signal on the media. A logic "0" is transmitted  
by the absence of the dipulse. During reception,  
the 200nS dipulse appearing on the media is  
coupled through the RF transformer of the LAN  
Driver, which produces a positive pulse at the  
RXIN pin of the COM20020. The pulse on the  
RXIN pin represents a logic "1". Lack of pulse  
represents a logic "0". Typically, RXIN pulses  
occur at multiples of 400nS. The COM20020  
can tolerate distortion of plus or minus 100nS  
and still correctly capture and convert the RXIN  
pulses to NRZ format. Figure 5 illustrates the  
events which occur in transmission or  
The Backplane Configuration does not isolate  
the node from the media nor protects it from  
Common Mode noise, but Common Mode Noise  
is less of a problem in short distances.  
The COM20020 supplies  
a
programmable  
output driver for Backplane Mode operation. A  
push/pull or open drain driver can be selected  
by programming the P1MODE bit of the Setup  
Register (see register descriptions for details.)  
The COM20020 defaults to an open drain  
output.  
The Backplane Configuration provides for direct  
connection between the COM20020 and the  
media. Only one pull-up resistor (in open drain  
configuration of the output driver) is required  
somewhere on the media (not on each  
individual node). The nPULSE1 signal, in this  
mode, is an open drain or push/pull driver and is  
used to directly drive the media. It issues a  
200nS negative pulse to transmit a logic "1". ote  
that when used in the open-drain mode, the  
COM20020 does not have a fail/safe input on  
the RXIN pin. The nPULSE1 signal actually  
contains a weak pull-up resistor. This pull-up  
should not take the place of the resistor  
required on the media for open drain mode.  
1
Please refer to TN7-5 - Cabling Guidelines  
for the COM20020 ULANC, available from  
SMSC, for recommended cabling distance,  
termination, and node count for ARCNET nodes.  
15  
 
RT  
RT  
+VCC  
+VCC  
+VCC  
RBIAS  
RBIAS  
RBIAS  
75176B or  
Equiv.  
COM20020  
COM20020  
COM20020  
FIGURE 4 - COM20020 NETWORK USING RS-485 DIFFERENTIAL TRANSCEIVERS  
1
1
0
20MHZ  
CLOCK  
(FOR REF.  
ONLY)  
100ns  
nPULSE1  
100ns  
nPULSE2  
200ns  
DIPULSE  
RXIN  
400ns  
FIGURE 5 - DIPULSE WAVEFORM FOR DATA OF 1-1-0  
16  
 
In typical applications, the serial backplane is  
terminated at both ends and a bias is provided  
by the external pull-up resistor.  
The Differential Driver Configuration cannot  
communicate directly with nodes utilizing the  
Traditional Hybrid Configuration.  
Like the  
Backplane Configuration, the Differential Driver  
Configuration does not isolate the node from the  
media.  
The RXIN signal is directly connected to the  
cable via an internal Schmitt trigger. A negative  
pulse on this input indicates a logic "1". Lack of  
pulse indicates a logic "0". For typical single-  
ended backplane applications, RXIN is  
connected to nPULSE1 to make the serial  
backplane data line. A ground line (from the  
coax or twisted pair) should run in parallel with  
the signal. For applications requiring different  
treatment of the receive signal (like filtering or  
squelching), nPULSE1 and RXIN remain as  
The Differential Driver interface includes a  
RS485 Driver/Receiver to transfer the data  
between the cable and the COM20020. The  
nPULSE1 signal transmits the data, provided  
the Transmit Enable signal is active. The  
nPULSE1 signal issues a 200nS negative pulse  
to transmit a logic "1". Lack of pulse indicates  
a logic "0". The RXIN signal receives the data,  
the transmitter portion of the COM20020 is  
disabled during reset and the nPULSE1,  
nPULSE2 and nTXEN pins are inactive.  
independent pins.  
External differential  
drivers/receivers for increased range and  
common mode noise rejection, for example,  
would require the signals to be independent of  
one another. When the device is in Backplane  
Mode, the clock provided by the nPULSE2  
signal may be used for encoding the data into a  
different encoding scheme or other synchronous  
operations needed on the serial data stream.  
Programmable TXEN Polarity  
To accommodate transceivers with active high  
ENABLE pins, the COM20020 contains  
a
programmable TXEN output. To program the  
TXEN pin for an active high pulse, the nPULSE2  
pin should be connected to ground. To retain  
the normal active low polarity, nPULSE2 should  
be left open. The polarity determination is made  
at power on reset and is valid only for Backplane  
Mode operation. The nPULSE2 pin should  
remain grounded at all times if an active high  
polarity is desired.  
Differential Driver Configuration  
The Differential Driver Configuration is a special  
case of the Backplane Mode. It is a dc coupled  
configuration recommended for applications like  
car-area networks or other cost-sensitive  
applications which do not require direct  
compatibility with existing ARCNET nodes and  
do not require isolation.  
17  
 
A0/n  
MU  
X
A1  
A2/B  
ALE  
ADDRESS  
DECODING  
CIRCUITRY  
2K x 8  
RAM  
ADDITIONAL  
REGISTERS  
AD0-AD2,  
D3-D7  
STATUS/  
COMMAND  
REGISTER  
nINTR  
nPULSE1  
nPULSE2  
nTXEN  
MICRO-  
TX/RX  
LOGIC  
SEQUENCER  
AND  
WORKING  
REGISTERS  
RXIN  
RESET  
LOGIC  
nRESET IN  
XTAL1  
XTAL2  
OSCILLATOR  
nRD/nDS  
nWR/DIR  
nCS  
BUS  
ARBITRATION  
CIRCUITRY  
RECONFIGURATION  
TIMER  
NODE ID  
LOGIC  
FIGURE 6 - INTERNAL BLOCK DIAGRAM  
18  
 
Table 1 - Typical Media  
ATTENUATION  
PER 1000 FT.  
AT 5MHZ  
NOMINAL  
IMPEDANCE  
CABLE TYPE  
RG-62 Belden #86262  
RG-59/U Belden #89108  
RG-11/U Belden #89108  
IBM Type 1* Belden #89688  
5.5dB  
7.0dB  
5.5dB  
7.0dB  
93W  
75W  
75W  
150W  
IBM Type 3* Telephone Twisted  
Pair Belden #1155A  
17.9dB  
16.0dB  
100W  
COMCODE 26 AWG Twisted  
Pair Part #105-064-703  
105W  
*Non-plenum-rated cables of this type are also available.  
Note: For more detailed information on Cabling options including RS-485, transformer-coupled RS-  
485 and Fiber Optic interfaces, please refer to TN7-5 - Cabling Guidelines for the COM20020  
ULANC, available from Standard Microsystems Corporation.  
FUNCTIONAL DESCRIPTION  
instructions are fetched and then placed into the  
instruction registers. One register holds the  
opcode, while the other holds the immediate  
data. Once the instruction is fetched, it is  
decoded by the internal instruction decoder, at  
which point the COM20020 proceeds to execute  
the instruction. When a no-op instruction is  
encountered, the microsequencer enters a timed  
loop and the program counter is temporarily  
stopped until the loop is complete. When a jump  
instruction is encountered, the program counter  
is loaded with the jump address from the ROM.  
MICROSEQUENCER  
The COM20020  
microsequencer which performs all of the  
control operations necessary to carry out the  
ARCNET protocol.  
generator, a 544 x 8 ROM, a program counter,  
two instruction registers, an instruction decoder,  
contains  
an  
internal  
It consists of a clock  
a
no-op  
generator,  
jump  
logic,  
and  
reconfiguration logic.  
The COM20020 derives a 5MHz and a 2.5MHz  
clock from the external crystal. These clocks  
provide the rate at which the instructions are  
executed within the COM20020. The 5MHz  
clock is the rate at which the program counter  
operates, while the 2.5MHz clock is the rate at  
which the instructions are executed. The  
microprogram is stored in the ROM and the  
The  
COM20020  
contains  
an  
internal  
reconfiguration timer which interrupts the  
microsequencer if it has timed out. At this point  
the program counter is cleared and the  
MYRECON bit of the Diagnostic Status Register  
is set.  
19  
 
Table 2 - Read Register Summary  
READ  
REGISTER  
STATUS  
MSB  
LSB  
ADDRESS  
00  
RI  
X
X
POR  
TEST RECON  
TMA  
TA  
MY-  
RECON  
DIAG.  
NEW  
NEXTID  
DUPID RCVACT TOKEN EXCNAK TENTID  
AUTO-  
01  
02  
X
STATUS  
ADDRESS  
PTR HIGH  
RDDATA  
X
X
X
A10  
A9  
A8  
INC  
ADDRESS  
PTR LOW  
A7  
D7  
X
A6  
A5  
D5  
X
A4  
D4  
A3  
D3  
A2  
D2  
X
03  
04  
A1  
D1  
A0  
D0  
D6  
X
DATA  
X
X
X
X
05  
06  
RESERVED  
BACK- SUB-  
PLANE  
SUB-  
AD0  
CONFIG-  
URATION  
RESET CCHEN TXEN  
ET1  
ET2  
AD1  
TENTID  
NODEID  
TID7  
NID7  
TID6  
NID6  
TID5  
NID5  
TID4  
NID4  
TID3  
NID3  
TID2  
NID2  
TID1  
NID1  
TID0  
NID0  
07  
SLOW  
ARB  
FOUR  
NAKS  
RCV_  
ALL  
SETUP  
P1MODE  
ET3  
CKP3  
CKP2  
CKP1  
NEXT ID  
NXTID7 NXTID6 NXTID5 NXTID4 NXTID3 NXTID2 NXTID1 NXTID0  
20  
 
Table 3 - Write Register Summary  
WRITE  
REGISTER  
ADDRESS  
00  
MSB  
LSB  
NEW  
NEXTID  
INTERRUPT  
MASK  
0
D4  
0
EXCNAK  
RI  
0
0
D5  
0
RECON  
D2  
TA  
D7  
RDDATA  
A7  
D6  
D3  
0
D1  
A9  
D0 COMMAND  
01  
02  
03  
04  
ADDRESS  
PTR HIGH  
AUTO-  
INC  
A10  
A2  
A8  
ADDRESS  
A6  
D6  
0
A5  
D5  
0
A4  
D4  
0
A3  
D3  
0
A1  
D1  
A0  
PTR LOW  
D0  
0
DATA  
D7  
D2  
0
RESERVED  
05  
06  
0
0
CONFIG-  
URATION  
BACK-  
PLANE  
SUB-  
AD1  
SUB-  
AD0  
RESET CCHEN TXEN  
ET1  
ET2  
TENTID  
NODEID  
TID7  
NID7  
TID6  
NID6  
TID5  
NID5  
TID4  
NID4  
TID3  
NID3  
TID2  
NID2  
TID1  
NID1  
TID0  
NID0  
07  
SLOW  
ARB  
FOUR  
NAKS  
RCV_  
ALL  
SETUP  
P1MODE  
0
ET3  
0
CKP3  
0
CKP2  
0
CKP1  
0
NEXT ID  
0
0
0
21  
 
INTERNAL REGISTERS  
loaded with the contents of COM20020 Internal  
Memory upon writing Address Pointer low only  
once.  
The COM20020 contains eight internal registers.  
Tables  
register map. Reserved locations should not be  
accessed. All undefined bits are read as  
2
and  
3
illustrate the COM20020  
Tentative ID Register  
undefined and must be written as logic "0".  
The Tentative ID Register is a read/write 8-bit  
register accessed when the Sub Address Bits  
are set up accordingly (please refer to the  
Interrupt Mask Register (IMR)  
Configuration Register).  
The Tentative ID  
The COM20020 is capable of generating an  
interrupt signal when certain status bits become  
true. A write to the IMR specifies which status  
bits will be enabled to generate an interrupt. The  
bit positions in the IMR are in the same position  
as their corresponding status bits in the Status  
Register and Diagnostic Status Register. A logic  
Register can be used while the node is on-line  
to build a network map of those nodes existing  
on the network. It minimizes the need for  
operator interaction with the network. The node  
determines the existence of other nodes by  
placing a Node ID value in the Tentative ID  
Register and waiting to see if the Tentative ID  
bit of the Diagnostic Status Register gets set.  
The network map developed by this method is  
only valid for a short period of time, since nodes  
may join or depart from the network at any time.  
When using the Tentative ID feature, a node  
cannot detect the existence of the next logical  
node to which it passes the token. The Next ID  
Register will hold the ID value of that node. The  
Tentative ID Register defaults to the value 0000  
0000 upon hardware reset only.  
"1" in  
a
particular position enables the  
corresponding interrupt. The Status bits capable  
of generating an interrupt include the Receiver  
Inhibited bit, New Next ID bit, Excessive NAK  
bit, Reconfiguration Timer bit, and Transmitter  
Available bit. No other Status or Diagnostic  
Status bits can generate an interrupt.  
The five maskable status bits are ANDed with  
their respective mask bits, and the results are  
ORed to produce the interrupt signal. An RI  
or TA interrupt is masked when the  
corresponding mask bit is reset to logic "0", but  
will reappear when the corresponding mask bit  
is set to logic "1" again, unless the interrupt  
status condition has been cleared by this time.  
A RECON interrupt is cleared when the "Clear  
Node ID Register  
The Node ID Register is a read/write 8-bit  
register accessed when the Sub Address Bits  
are set up accordingly (please refer to the  
Configuration Register). The Node ID Register  
contains the unique value which identifies this  
particular node. Each node on the network  
must have a unique Node ID value at all times.  
The Duplicate ID bit of the Diagnostic Status  
Register helps the user find a unique Node ID.  
Refer to the Initialization Sequence section for  
further detail on the use of the DUPID bit. The  
core of the COM20020 does not wake up until a  
Node ID other than zero is written into the Node  
ID Register. During this time, no microcode is  
executed, no tokens are passed by this node,  
and no reconfigurations are caused by this  
node. Once a non-zero NodeID is placed into  
the Node ID Register, the core wakes up but will  
not join the network until the TXEN bit of the  
Flags" command is issued.  
An EXCNAK  
interrupt is cleared when the "POR Clear Flags"  
command is issued. A New Next ID interrupt is  
cleared by reading the Next ID Register. The  
Interrupt Mask Register defaults to the value  
0000 0000 upon hardware reset.  
Data Register  
This read/write 8-bit register is used as the  
channel through which the data to and from the  
RAM passes. The data is placed in or retrieved  
from the address location presently specified by  
the address pointer. The contents of the Data  
Register are undefined upon hardware reset. In  
case of READ operation, the Data Register is  
Configuration Register is set.  
While the  
22  
 
Transmitter is disabled, the Receiver portion of  
the device is still functional and will provide the  
user with useful information about the network.  
The Node ID Register defaults to the value 0000  
0000 upon hardware reset only.  
Chaining operation.  
defaults to the value 1XX1 0001 upon either  
hardware or software reset.  
The Status Register  
Diagnostic Status Register  
Next ID Register  
The Diagnostic Status Register contains seven  
read-only bits which help the user troubleshoot  
the network or node operation. Various  
combinations of these bits and the TXEN bit of  
the Configuration Register represent different  
The Next ID Register is an 8-bit, read-only  
register, accessed when the sub-address bits  
are set up accordingly (please refer to the  
Configuration Register). The Next ID Register  
holds the value of the Node ID to which the  
COM20020 will pass the token. When used in  
conjunction with the Tentative ID Register, the  
situations.  
All of these bits, except the  
Excessive NAcK bit and the New Next ID bit, are  
reset to logic "0" upon reading the Diagnostic  
Status Register or upon software or hardware  
reset. The EXCNAK bit is reset by the "POR  
Clear Flags" command or upon software or  
hardware reset. The Diagnostic Status Register  
defaults to the value 0000 000X upon either  
hardware or software reset.  
Next ID Register can provide  
a
complete  
network map. The Next ID Register is updated  
each time a node enters/leaves the network or  
when a network reconfiguration occurs. Each  
time the microsequencer updates the Next ID  
Register, a New Next ID interrupt is generated.  
This bit is cleared by reading the Next ID  
Register. Default value is 0000 0000 upon  
hardware or software reset.  
Command Register  
Execution of commands are initiated by  
performing microcontroller writes to this  
register. Any combinations of written data  
other than those listed in Table 6 are not  
permitted and may result in incorrect chip  
and/or network operation.  
Status Register  
The COM20020 Status Register is an 8-bit read-  
only register. All of the bits, except for bits 5  
and 6, are software compatible with previous  
SMSC ARCNET devices. In previous SMSC  
ARCNET devices the Extended Timeout status  
was provided in bits 5 and 6 of the Status  
Register. In the COM20020, the COM90C66,  
Address Pointer Registers  
These read/write registers are each 8-bits wide  
and are used for addressing the internal RAM.  
New pointer addresses should be written by first  
writing to the High Register and then writing to  
the Low Register because writing to the Low  
Register loads the address. The contents of the  
Address Pointer High and Low Registers are  
undefined upon hardware reset. Writing to  
Address Pointer low loads the address.  
and  
the  
COM90C165,  
COM20020-5,  
COM20051 and COM20051+ these bits exist in  
and are controlled by the Configuration Register.  
The Status Register contents are defined as in  
Table 4, but are defined differently during the  
Command Chaining operation. Please refer to  
the Command Chaining section for the definition  
of the Status Register during Command  
23  
 
Configuration Register  
Setup Register  
The Configuration Register is  
a
read/write  
The Setup Register is a read/write 8-bit register  
accessed when the Sub Address Bits are set up  
accordingly (see the bit definitions of the  
Configuration Register). The Setup Register  
allows the user to change the network speed  
register which is used to configure the different  
modes of the COM20020. The Configuration  
Register defaults to the value 0001 1000 upon  
hardware reset only. SUBAD0 and SUBAD1  
point to selection in Register 7.  
(data  
rate)  
or  
the arbitration  
speed  
independently, invoke the Receive All feature,  
change the nPULSE1 driver type, and reduce  
protocol timeouts by a factor of 3. The data rate  
may be slowed to 156.25Kbps and/or the  
arbitration speed may be slowed by a factor of  
two. The Setup Register defaults to the value  
0000 0000 upon hardware reset only.  
24  
 
Table 4 - Status Register  
DESCRIPTION  
BIT  
BIT NAME  
Receiver  
Inhibited  
SYMBOL  
RI  
7
This bit, if high, indicates that the receiver is not enabled because either  
an "Enable Receive to Page fnn" command was never issued, or a  
packet has been deposited into the RAM buffer page fnn as specified by  
the last "Enable Receive to Page fnn" command. No messages will be  
received until this command is issued, and once the message has been  
received, the RI bit is set, thereby inhibiting the receiver. The RI bit is  
cleared by issuing an "Enable Receive to Page fnn" command. This bit,  
when set, will cause an interrupt if the corresponding bit of the Interrupt  
Mask Register (IMR) is also set. When this bit is set and another  
station attempts to send a packet to this station, this station will send a  
NAK.  
6,5 (Reserved)  
These bits are undefined.  
4
Power On Reset  
POR  
This bit, if high, indicates that the COM20020 has been reset by either a  
software reset, a hardware reset, or writing 00H to the Node ID  
Register. The POR bit is cleared by the "Clear Flags" command.  
3
2
Test  
TEST  
This bit is intended for test and diagnostic purposes. It is a logic "0"  
under normal operating conditions.  
Reconfiguration  
RECON  
This bit, if high, indicates that the Line Idle Timer has timed out because  
the RXIN pin was idle for 82mS. The RECON bit is cleared during a  
"Clear Flags" command. This bit, when set, will cause an interrupt if the  
corresponding bit in the IMR is also set. The interrupt service routine  
should consist of examining the MYRECON bit of the Diagnostic Status  
Register to determine whether there are consecutive reconfigurations  
caused by this node.  
1
0
Transmitter  
Message  
Acknowledged  
TMA  
TA  
This bit, if high, indicates that the packet transmitted as a result of an  
"Enable Transmit from Page fnn" command has been acknowledged.  
This bit should only be considered valid after the TA bit (bit 0) is set.  
Broadcast messages are never acknowledged. The TMA bit is cleared  
by issuing the "Enable Transmit from Page fnn" command.  
Transmitter  
Available  
This bit, if high, indicates that the transmitter is available for  
transmitting. This bit is set when the last byte of scheduled packet has  
been transmitted out, or upon execution of a "Disable Transmitter"  
command. The TA bit is cleared by issuing the "Enable Transmit from  
Page fnn" command after the node next receives the token. This bit,  
when set, will cause an interrupt if the corresponding bit in the IMR is  
also set.  
25  
 
Table 5 - Diagnostic Status Register  
SYMBOL DESCRIPTION  
BIT  
BIT NAME  
7
My Reconfiguration MY-  
This bit, if high, indicates that a past reconfiguration was caused by this  
node. It is set when the Lost Token Timer times out, and should be typically  
read following an interrupt caused by RECON. Refer to the Improved  
Diagnostics section for further detail.  
RECON  
6
Duplicate ID  
DUPID  
This bit, if high, indicates that the value in the Node ID Register matches  
both Destination ID characters of the token and a response to this token has  
occurred. Trailing zero's are also verified. A logic "1" on this bit indicates a  
duplicate Node ID, thus the user should write a new value into the Node ID  
Register. This bit is only useful for duplicate ID detection when the device is  
off line, that is, when the transmitter is disabled. When the device is on line  
this bit will be set every time the device gets the token. This bit is reset  
automatically upon reading the Diagnostic Status Register. Refer to the  
Improved Diagnostics section for further detail.  
5
4
3
Receive  
Activity  
RCVACT  
TOKEN  
This bit, if high, indicates that data activity (logic "1") was detected on the  
RXIN pin of the device. Refer to the Improved Diagnostics section for  
further detail.  
Token Seen  
This bit, if high, indicates that a token has been seen on the network, sent by  
a node other than this one. Refer to the Improved Diagnostic section for  
further detail.  
Excessive NAK  
EXCNAK  
This bit, if high, indicates that either 128 or 4 Negative Acknowledgements  
have occurred in response to the Free Buffer Enquiry. This bit is cleared  
upon the "POR Clear Flags" command. Reading the Diagnostic Status  
Register does not clear this bit. This bit, when set, will cause an interrupt if  
the corresponding bit in the IMR is also set. Refer to the Improved  
Diagnostics section for further detail.  
2
1
Tentative ID  
New Next ID  
TENTID  
This bit, if high, indicates that a response to a token whose DID matches the  
value in the Tentative ID Register has occurred. The second DID and the  
trailing zero's are not checked. Since each node sees every token passed  
around the network, this feature can be used with the device on-line in order  
to build and update a network map. Refer to the Improved Diagnostics  
section for further detail.  
NEW  
NXTID  
This bit, if high, indicates that the Next ID Register has been updated and  
that a node has either joined or left the network. Reading the Diagnostic  
Status Register does not clear this bit. This bit, when set, will cause an  
interrupt if the corresponding bit in the IMR is also set. The bit is cleared by  
reading the Next ID Register.  
1,0 (Reserved)  
These bits are undefined.  
26  
 
Table 6 - Command Register  
DESCRIPTION  
DATA  
COMMAND  
0000 0000  
Clear  
Transmit  
Interrupt  
This command is used only in the Command Chaining operation. Please  
refer to the Command Chaining section for definition of this command.  
0000 0001  
0000 0010  
Disable  
Transmitter  
This command will cancel any pending transmit command (transmission  
that has not yet started) and will set the TA (Transmitter Available) status  
bit to logic "1" when the COM20020 next receives the token.  
Disable  
This command will cancel any pending receive command.  
If the  
Receiver  
COM20020 is not yet receiving a packet, the RI (Receiver Inhibited) bit will  
be set to logic "1" the next time the token is received. If packet reception is  
already underway, reception will run to its normal conclusion.  
b0fn n100  
Enable  
Receive to  
Page fnn  
This command allows the COM20020 to receive data packets into RAM  
buffer page fnn and resets the RI status bit to logic "0". The values placed  
in the "nn" bits indicate the page that the data will be received into (page 0,  
1, 2, or 3). If the value of "f" is a logic "1", an offset of 256 bytes will be  
added to that page specified in "nn", allowing a finer resolution of the  
buffer. Refer to the Selecting RAM Page Size section for further detail. If  
the value of "b" is logic "1", the device will also receive broadcasts  
(transmissions to ID zero). The RI status bit is set to logic "1" upon  
successful reception of a message.  
00fn n011  
Enable  
Transmit from  
Page fnn  
This command prepares the COM20020 to begin a transmit sequence  
from RAM buffer page fnn the next time it receives the token. The values  
of the "nn" bits indicate which page to transmit from (0, 1, 2, or 3). If "f" is  
logic "1", an offset of 256 bytes is the start of the page specified in "nn",  
allowing a finer resolution of the buffer. Refer to the Selecting RAM Page  
Size section for further detail. When this command is loaded, the TA and  
TMA bits are reset to logic "0". The TA bit is set to logic "1" upon  
completion of the transmit sequence. The TMA bit will have been set by  
this time if the device has received an ACK from the destination node. The  
ACK is strictly hardware level, sent by the receiving node before its  
microcontroller is even aware of message reception. Refer to Figure 1 for  
details of the transmit sequence and its relation to the TA and TMA status  
bits.  
0000 c101  
Define  
Configuration  
This command defines the maximum length of packets that may be  
handled by the device. If "c" is a logic "1", the device handles both long  
and short packets. If "c" is a logic "0", the device handles only short  
packets.  
000r p110  
0000 1000  
Clear Flags  
This command resets certain status bits of the COM20020. A logic "1" on  
"p" resets the POR status bit and the EXCNAK Diagnostic status bit.  
logic "1" on "r" resets the RECON status bit.  
A
Clear  
Receive  
Interrupt  
This command is used only in the Command Chaining operation. Please  
refer to the Command Chaining section for definition of this command.  
27  
 
Table 7 - Address Pointer High Register  
BIT  
BIT NAME  
Read Data  
SYMBOL  
DESCRIPTION  
7
RDDATA  
This bit tells the COM20020 whether the following access  
will be a read or write. A logic "1" prepares the device for  
a read, a logic "0" prepares it for a write.  
6
Auto Increment  
AUTOINC  
A10-A8  
This bit controls whether the address pointer will  
increment automatically. A logic "1" on this bit allows  
automatic increment of the pointer after each access,  
while a logic "0" disables this function. Please refer to  
the Sequential Access Memory section for further detail.  
5-3 (reserved)  
These bits are undefined.  
2-0 Address 10-8  
These bits hold the upper three address bits which  
provide addresses to RAM.  
Table 8 - Address Pointer Low Register  
BIT  
7-0  
BIT NAME  
Address 7-0  
SYMBOL  
DESCRIPTION  
A7-A0  
These bits hold the lower 8 address bits which provide  
the addresses to RAM.  
28  
 
Table 9 - Configuration Register  
SYMBOL DESCRIPTION  
BIT  
BIT NAME  
7
Reset  
RESET  
A software reset of the COM20020 is executed by writing a logic "1"  
to this bit. A software reset does not reset the microcontroller  
interface mode, nor does it affect the Configuration Register. The  
only registers that the software reset affect are the Status Register,  
the Next ID Register, and the Diagnostic Status Register. This bit  
must be brought back to logic "0" to release the reset.  
6
5
Command  
Chaining Enable  
CCHEN  
TXEN  
This bit, if high, enables the Command Chaining operation of the  
device. Please refer to the Command Chaining section for further  
details. A low level on this bit ensures software compatibility with  
previous SMSC ARCNET devices.  
Transmit Enable  
When low, this bit disables transmissions by keeping nPULSE1,  
nPULSE2 if in non-Backplane Mode, and nTXENABLE inactive.  
When high, it enables the above signals to be activated during  
transmissions. This bit defaults low upon reset. This bit is typically  
enabled once the Node ID is determined, and never disabled during  
normal operation. Please refer to the Improved Diagnostics section  
for details on evaluating network activity.  
4,3  
Extended  
Timeout 1,2  
ET1, ET2  
These bits allow the network to operate over longer distances than the  
default maximum 4 miles by controlling the Response, Idle, and  
Reconfiguration Times. All nodes should be configured with the  
same timeout values for proper network operation.  
For the  
COM20020 with a 20 MHz crystal oscillator, the bit combinations  
follow:  
Response  
Time (mS)  
1193.6  
596.8  
IdleTime  
(mS)  
1312  
656  
Reconfig  
Time (mS)  
1680  
ET2  
0
0
ET1  
0
1
1680  
1
0
1680  
298.4  
328  
1
1
840  
74.7  
82  
2
Backplane  
BACK-  
PLANE  
A logic "1" on this bit puts the device into Backplane Mode signalling  
which is used for Open Drain and Differential Driver interfaces.  
1,0  
Sub Address 1,0  
SUBAD 1,0 These bits determine which register at address 07 may be accessed.  
The combinations are as follows:  
SUBAD1  
SUBAD0 Register  
0
0
1
1
0
1
0
1
Tentative ID  
Node ID  
Setup  
Next ID  
29  
 
Table 10 - Setup Register  
SYMBOL DESCRIPTION  
BIT  
BIT NAME  
7
Pulse1 Mode  
P1MODE  
This bit determines the type of PULSE1 output driver used in  
Backplane Mode. When high, a push/pull output is used. When  
low, an open drain output is used. The default is open drain.  
6
5
4
Four NACKS  
FOUR  
NACKS  
This bit, when set, will cause the EXNACK bit in the Diagnostic  
Status Register to set after four NACKs to Free Buffer Enquiry are  
detected by the COM20020. This bit, when reset, will set the  
EXNACK bit after 128 NACKs to Free Buffer Enquiry. The default  
is 128.  
ET3  
ET3  
This bit, when set, scales down protocol timeout values of  
Response Time and Idle Time but not Reconfiguration Time to  
optimize network performance in short topologies. Provides a  
scaling factor of ¸ 3. Defaults to a zero. Must be reset to be  
ARCNET compliant.  
Receive All  
RCVALL  
This bit, when set, allows the COM20020 to receive all valid data  
packets on the network, regardless of their destination ID. This  
mode can be used to implement a network monitor with the  
transmitter on- or off-line. Note that ACKs are only sent for packets  
received with  
a
destination ID equal to the COM20020's  
programmed node ID. This feature can be used to put the  
COM20020 in a 'listen-only' mode, where the transmitter is disabled  
and the COM20020 is not passing tokens. Defaults low.  
3,2,1  
Clock Prescaler Bits  
3,2,1  
CKP3,2,1  
These bits are used to determine the data rate of the COM20020.  
The following table is for a 20MHz crystal:  
CKP3  
CKP2 CKP1  
DIVISOR  
SPEED  
2.5Mbs  
1.25Mbs  
625Kbs  
312.5Kbs  
156.25Kbs  
Reserved  
Reserved  
Reserved  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
16  
32  
64  
128  
256  
NOTE: The lowest data rate achievable by the COM20020 is  
156.25Kbs. A divide by 256 is provided for those systems that use  
faster clock speeds. Defaults to 000 or 2.5Mbs.  
0
Slow Arbitration Select SLW-ARB  
This bit, when set, will divide the arbitration clock by 2. Memory  
cycle times will increase when slow arbitration is selected.  
NOTE: For clock speeds greater than 20MHz, SLOWARB must be  
set. Defaults to low.  
30  
 
Data Register  
I/O Address 04H  
Memory  
Data Bus  
2K x 8  
INTERNAL  
RAM  
8
D0-D7  
Address Pointer Register  
I/O Address 02H I/O Address 03H  
High  
Low  
Memory  
Address Bus  
11-Bit Counter  
11  
FIGURE 7 - SEQUENTIAL ACCESS OPERATION  
31  
 
INTERNAL RAM  
continued until the entire packet is read out of  
RAM. Refer to Figure 7 for an illustration of the  
Sequential Access operation. When switching  
between reads and writes, the pointer must first  
be written with the starting address. At least  
one cycle time should separate the pointer being  
loaded and the first read (see timing  
parameters).  
The integration of the 2K x 8 RAM in the  
COM20020 represents significant real estate  
savings. The most obvious benefit is the 24-pin  
package in which the device is now placed (a  
direct result of the integration of RAM). In  
addition, the PC board is now free of the  
cumbersome external RAM, external latch, and  
multiplexed address/data bus and control  
functions which were necessary to interface to  
the RAM. The integration of RAM represents  
significant cost savings because it isolates the  
system designer from the changing costs of  
external RAM and it minimizes reliability  
problems, assembly time and costs, and layout  
complexity.  
Access Speed  
The COM20020 is able to accommodate very  
fast access cycles to its registers and buffers.  
Arbitration to the buffer does not slow down the  
cycle because the pointer based access method  
allows data to be prefetched from memory and  
stored in a temporary register. Likewise, data  
to be written is stored in the temporary register  
and then written to memory.  
Sequential Access Memory  
The internal RAM is accessed via a pointer-  
based scheme. Rather than interfering with  
system memory, the internal RAM is indirectly  
accessed through the Address High and Low  
Pointer Registers. The data is channeled to and  
from the microcontroller via the 8-bit data  
register. For example: a packet in the internal  
RAM buffer is read by the microcontroller by  
writing the corresponding address into the  
Address Pointer High and Low Registers (offsets  
02H and 03H). Note that the High Register  
should be written first, followed by the Low  
Register, because writing to the Low Register  
loads the address. At this point the device  
accesses that location and places the  
corresponding data into the data register. The  
microcontroller then reads the data register  
(offset 04H) to obtain the data at the specified  
location. If the Auto Increment bit is set to logic  
"1", the device will automatically increment the  
address and place the next byte of data into  
the data register, again to be read by the  
For systems which do not require quick access  
time, the arbitration clock may be slowed down  
by setting bit 0 of the Setup Register equal to  
logic "1". Since the Slow Arbitration feature  
divides the input clock by two, the duty cycle of  
the input clock may be relaxed.  
SOFTWARE INTERFACE  
The microcontroller interfaces to the COM20020  
via software by accessing the various registers.  
These actions are described in the Internal  
Registers section.  
The software flow for  
accessing the data buffer is based on the  
Sequential Access scheme.  
sequence is as follows:  
The basic  
·
·
Disable Interrupts  
Write to Pointer Register High (specifying  
Auto-Increment mode.)  
·
Write to Pointer Register Low (this loads  
the address.)  
·
·
Enable Interrupts  
microcontroller.  
This  
process  
is  
Read or write the Data Register (repeat as  
many times as necessary to empty or fill  
the buffer).  
32  
 
·
The pointer may now be read to determine  
how many transfers were completed.  
If the device is configured to handle both long  
and short packets (see "Define Configuration"  
command), then receive pages should always  
be 512 bytes long because the user never  
knows what the length of the receive packet will  
be. In this case, the transmit pages may be  
made 256 bytes long, leaving at least 512 bytes  
free at any given time. Even if the Command  
Chaining operation is being used, 512 bytes is  
still guaranteed to be free because Command  
Chaining only requires two pages for transmit  
and two for receive (in this case, two 256 byte  
pages for transmit and two 512 byte pages for  
receive, leaving 512 bytes free). Please note  
that it is the responsibility of software to reserve  
512 bytes for each receive page if the device is  
The software flow for controlling the  
Configuration, Node ID, Tentative ID, and Next  
ID registers is generally limited to the  
initialization sequence and the maintenance of  
the network map.  
Additionally, it is necessary to understand the  
details of how the other Internal Registers are  
used in the transmit and receive sequences and  
to know how the internal RAM buffer is properly  
set up. The sequence of events that tie these  
actions together is discussed as follows.  
Selecting RAM Page Size  
configured to handle long packets.  
The  
COM20020 does not check page boundaries  
during reception. If the device is configured to  
handle only short packets, then both transmit  
and receive pages may be allocated as 256  
bytes long, freeing at least 1KByte at any given  
time.  
During normal operation, the 2K x 8 of RAM is  
divided into four pages of 512 bytes each. The  
page to be used is specified in the "Enable  
Transmit (Receive) from (to) Page fnn"  
command, where "nn" specifies page 0, 1, 2, or  
3. This allows the user to have constant control  
over the allocation of RAM.  
Even if the Command Chaining operation is  
being used, 1KByte is still guaranteed to be free  
because Command Chaining only requires two  
pages for transmit and two for receive (in this  
case, a total of four 256 byte pages, leaving 1K  
free).  
When the Offset bit "f" (bit 5 of the "Enable  
Transmit (Receive) from (to) Page fnn"  
command word) is set to logic "1", an offset of  
256 bytes is added to the page specified. For  
example: to transmit from the second half of  
page 0, the command "Enable Transmit from  
Page fnn" (fnn=100 in this case) is issued by  
writing 0010 0011 to the Command Register.  
This allows a finer resolution of the buffer pages  
without affecting software compatibility. This  
scheme is useful for applications which  
frequently use packet sizes of 256 bytes or less,  
especially for microcontroller systems with  
The general rule which may be applied to  
determine where in RAM a page begins is as  
follows:  
Address = (nn x 512) + (f x 256).  
Transmit Sequence  
During a transmit sequence, the microcontroller  
selects a 256 or 512 byte segment of the RAM  
buffer and writes into it. The appropriate buffer  
size is specified in the "Define Configuration"  
command. When long packets are enabled, the  
COM20020 interprets the packet as either a  
long or short packet, depending on whether the  
limited memory capacity.  
The remaining  
portions of the buffer pages which are not  
allocated for current transmit or receive packets  
may be used as temporary storage for previous  
network data, packets to be sent later, or as  
extra memory for the system, which may be  
indirectly accessed.  
33  
 
LONG PACKET  
FORMAT  
SHORT PACKET  
FORMAT  
ADDRESS  
0
ADDRESS  
0
SID  
DID  
SID  
DID  
1
2
1
2
3
COUNT = 256-N  
0
COUNT = 512-N  
NOT USED  
COUNT  
DATA BYTE 1  
DATA BYTE 2  
NOT USED  
COUNT  
DATA BYTE 1  
DATA BYTE 2  
DATA BYTE N-1  
DATA BYTE N  
255  
511  
DATA BYTE N-1  
DATA BYTE N  
NOT USED  
511  
N = DATA PACKET LENGTH  
SID = SOURCE ID  
DID = DESTINATION ID  
(DID = 0 FOR BROADCASTS)  
FIGURE 8 - RAM BUFFER PACKET CONFIGURATION  
34  
 
buffer address 2 contains a zero or non-zero  
value. The format of the buffer is shown in  
the microcontroller may issue the "Enable  
Transmit from Page fnn" command, which  
resets the TA and TMA bits to logic "0". If the  
message is not a BROADCAST, the COM20020  
Figure 8.  
Address 0 contains the Source  
contains the  
Identifier (SID); Address  
1
Destination Identifier (DID); Address 2 (COUNT)  
contains, for short packets, the value 256-N,  
where N represents the number of information  
bytes in the message, or for long packets, the  
value 0, indicating that it is indeed a long  
packet. In the latter case, Address 3 (COUNT)  
automatically sends  
a
FREE BUFFER  
ENQUIRY to the destination node in order to  
send the message. At this point, one of four  
possibilities may occur.  
The first possibility is if a free buffer is available  
at the destination node, in which case it  
responds with an ACKnowledgement. At this  
point, the COM20020 fetches the data from the  
Transmit Buffer and performs the transmit  
sequence. If a successful transmit sequence is  
completed, the TMA bit and the TA bit are set to  
logic "1". If the packet was not transmitted  
successfully, TMA will not be set. A successful  
transmission occurs when the receiving node  
responds to the packet with an ACK. An  
unsuccessful transmission occurs when the  
receiving node does not respond to the packet.  
would contain the value 512-N, where  
N
represents the number of information bytes in  
the message. The SID in Address 0 is used by  
the receiving node to reply to the transmitting  
node. The COM20020 puts the local ID in this  
location, therefore it is not necessary to write  
into this location.  
Please note that a short packet may contain  
between 1 and 253 data bytes, while a long  
packet may contain between 257 and 508 data  
bytes. A minimum value of 257 exists on a long  
packet so that the COUNT is expressable in  
eight bits. This leaves three exception packet  
lengths which do not fit into either a short or  
long packet; packet lengths of 254, 255, or 256  
bytes. If packets of these lengths must be sent,  
the user must add dummy bytes to the packet  
in order to make the packet fit into a long  
packet.  
The second possibility is if the destination node  
responds to the Free Buffer Enquiry with a  
Negative AcKnowledgement. A NAK occurs  
when the RI bit of the destination node is a logic  
"1". In this case, the token is passed on from  
the transmitting node to the next node. The next  
time the transmitter receives the token, it will  
again transmit a FREE BUFFER ENQUIRY. If a  
NAK is again received, the token is again  
passed onto the next node. The Excessive NAK  
bit of the Diagnostic Status Register is used to  
prevent an endless sending of FBE's and NAK's.  
If no limit of FBE-NAK sequences existed, the  
transmitting node would continue issuing a Free  
Buffer Enquiry, even though it would  
continuously receive a NAK as a response. The  
EXCNAK bit generates an interrupt (if enabled)  
in order to tell the microcontroller to disable the  
transmitter via the "Disable Transmitter"  
command. This causes the transmission to be  
abandoned and the TA bit to be set to a logic "1"  
when the node next receives the token, while the  
TMA bit remains at a logic "0". Please refer to  
the Improved Diagnostics section for further  
detail on the EXCNAK bit.  
Once the packet is written into the buffer, the  
microcontroller awaits a logic "1" on the TA bit,  
indicating that a previous transmit command  
has concluded and another may be issued.  
Each time the message is loaded and a transmit  
command issued, it will take a variable amount  
of time before the message is transmitted,  
depending on the traffic on the network and the  
location of the token at the time the transmit  
command was issued. The conclusion of the  
Transmit Command will generate an interrupt if  
the Interrupt Mask allows it. If the device is  
configured for the Command Chaining  
operation, please see the Command Chaining  
section for further detail on the transmit  
sequence. Once the TA bit becomes a logic "1",  
35  
 
The third possibility which may occur after a  
FREE BUFFER ENQUIRY is issued is if the  
destination node does not respond at all. In this  
case, the TA bit is set to a logic "1", while the  
TMA bit remains at a logic "0". The user should  
determine whether the node should try to  
reissue the transmit command.  
microcontroller will be interrupted if the  
corresponding bit in the Interrupt Mask Register  
is set to logic "1".  
Otherwise, the  
microcontroller must periodically check the  
Status Register. Once the microcontroller is  
alerted to the fact that the previous reception  
has concluded, it may issue the "Enable  
Receive to Page fnn" command, which resets  
the RI bit to logic "0" and selects a new page in  
the RAM buffer. Again, the appropriate buffer  
size is specified in the "Define Configuration"  
The fourth possibility is if a non-traditional  
response is received (some pattern other than  
ACK or NAK, such as noise). In this case, the  
token is not passed onto the next node, which  
causes the Lost Token Timer of the next node to  
command.  
Typically, the page which just  
received the data packet will be read by the  
microcontroller at this point. Once the "Enable  
Receive to Page fnn" command is issued, the  
microcontroller attends to other duties. There is  
no way of knowing how long the new reception  
will take, since another node may transmit a  
packet at any time. When another node does  
transmit a packet to this node, and if the  
"Define Configuration" command has enabled  
the reception of long packets, the COM20020  
interprets the packet as either a long or short  
packet, depending on whether the content of the  
buffer location 2 is zero or non-zero. The format  
of the buffer is shown in Figure 8. Address 0  
contains the Source Identifier (SID), Address 1  
contains the Destination Identifier (DID), and  
Address 2 contains, for short packets, the value  
256-N, where N represents the message length,  
or for long packets, the value 0, indicating that it  
is indeed a long packet. In the latter case,  
Address 3 contains the value 512-N, where N  
represents the message length. Note that on  
reception, the COM20020 deposits packets into  
the RAM buffer in the same format that the  
transmitting node arranges them, which allows  
time out, thus generating  
reconfiguration.  
a
network  
The "Disable Transmitter" command may be  
used to cancel any pending transmit command  
when the COM20020 next receives the token.  
Normally, in an active network, this command  
will set the TA status bit to a logic "1" when the  
token is received. If the "Disable Transmitter"  
command does not cause the TA bit to be set in  
the time it takes the token to make a round trip  
through the network, one of three situations  
exists. Either the node is disconnected from the  
network, or there are no other nodes on the  
network, or the external receive circuitry has  
failed. These situations can be determined by  
either using the improved diagnostic features of  
the COM20020 or using another software  
timeout which is greater than the worst case  
time for a round trip token pass, which occurs  
when all nodes transmit a maximum length  
message.  
Receive Sequence  
for  
a
message to be received and then  
A receive sequence begins with the RI status bit  
becoming a logic "1", which indicates that a  
retransmitted without rearranging any bytes in  
the RAM buffer other than the SID and DID.  
Once the packet is received and stored correctly  
in the selected buffer, the COM20020 sets the  
RI bit to logic "1" to signal the microcontroller  
that the reception is complete.  
previous reception has concluded.  
The  
36  
 
M S B  
TRI  
LSB  
R I  
TA  
POR  
TEST  
RECON  
TMA  
TMA  
TTA  
TRI  
TTA  
FIGURE 9 - COMMAND CHAINING STATUS REGISTER QUEUE  
·
Up to two outstanding transmit interrupts  
and two outstanding receive interrupts are  
stored by the device, along with their  
respective status bits.  
COMMAND CHAINING  
The Command Chaining operation allows  
consecutive transmissions and receptions to  
occur without host microcontroller intervention.  
Through the use of a dual two-level FIFO,  
commands to be transmitted and received, as  
well as the status bits, are pipelined.  
·
The Interrupt Mask bits act on TTA (Rising  
Transition on Transmitter Available) for  
transmit operations and TRI (Rising  
Transition of Receiver Inhibited) for receive  
operations. TTA is set upon completion of  
a packet transmission only. TRI is set upon  
completion of a packet reception only.  
Typically there is no need to mask the TTA  
and TRI bits after clearing the interrupt.  
In order for the COM20020 to be compatible  
with previous SMSC ARCNET device drivers,  
the device defaults to the non-chaining mode.  
In order to take advantage of the Command  
Chaining operation, the Command Chaining  
Mode must be enabled via a logic "1" on bit 6 of  
the Configuration Register.  
·
The traditional TA and RI bits are still  
available to reflect the present status of the  
device.  
In Command Chaining, the Status Register  
appears as in Figure 9.  
Transmit Command Chaining  
When the processor issues the first "Enable  
Transmit to Page fnn" command, the  
COM20020 responds in the usual manner by  
resetting the TA and TMA bits to prepare for the  
transmission from the specified page. The TA  
bit can be used to see if there is currently a  
transmission pending, but the TA bit is really  
meant to be used in the non-chaining mode  
The following is a list of Command Chaining  
guidelines for the software programmer. Further  
detail can be found in the Transmit Command  
Chaining and Receive Command Chaining  
sections.  
·
The device is designed such that the interrupt  
service routine latency does not affect  
performance.  
only.  
The TTA bits provide the relevant  
information for the device in the Command  
Chaining mode.  
·
Up to two outstanding transmissions and two  
outstanding receptions can be pending at any  
given time. The commands may be given in  
any order.  
37  
 
In the Command Chaining Mode, at any time  
after the first command is issued, the processor  
can issue a second "Enable Transmit from Page  
fnn" command. The COM20020 stores the fact  
that the second transmit command was issued,  
along with the page number.  
the Status Register will again be updated with  
the results of the second transmission and a  
second interrupt resulting from the second  
transmission will occur.  
The COM20020  
guarantees minimum of 200ns interrupt  
a
inactive time interval before the following edge.  
After the first transmission is completed, the  
COM20020 updates the Status Register by  
setting the TTA bit, which generates an  
interrupt. The interrupt service routine should  
read the Status Register. At this point, the TTA  
bit will be found to be a logic "1" and the TMA  
(Transmit Message Acknowledge) bit will tell the  
processor whether the transmission was  
successful. After reading the Status Register,  
the "Clear Transmit Interrupt" command is  
issued, thus resetting the TTA bit and clearing  
The Transmitter Available (TA) bit of the  
Interrupt Mask Register now masks only the  
TTA bit of the Status Register, not the TA bit as  
in the non-chaining mode. Since the TTA bit is  
only set upon transmission of a packet (not by  
RESET), and since the TTA bit may easily be  
reset by issuing a "Clear Transmit Interrupt"  
command, there is no need to use the TA bit of  
the Interrupt Mask Register to mask interrupts  
generated by the TTA bit of the Status Register.  
the interrupt.  
Note that only the "Clear  
In Command Chaining mode mode, the  
"Disable Transmitter" command will cancel the  
oldest transmission. This permits canceling a  
packet destined for a node not ready to receive.  
If both packets should be canceled, two  
"Disable Transmitter" commands should be  
issued.  
Transmit Interrupt" command will clear the TTA  
bit and the interrupt. It is not necessary,  
however, to clear the bit or the interrupt right  
away because the status of the transmit  
operation is double buffered in order to retain  
the results of the first transmission for analysis  
by the processor. This information will remain  
in the Status Register until the "Clear Transmit  
Interrupt" command is issued. Note that the  
interrupt will remain active until the command is  
issued, and the second interrupt will not occur  
until the first interrupt is acknowledged. The  
COM20020 guarantees a minimum of 200nS  
interrupt inactive time interval between  
interrupts. The TMA bit is also double buffered  
to reflect whether the appropriate transmission  
was a success. The TMA bit should only be  
considered valid after the corresponding TTA bit  
has been set to a logic "1". The TMA bit never  
causes an interrupt.  
Receive Command Chaining  
Like the Transmit Command Chaining  
operation, the processor can issue two  
consecutive "Enable Receive from Page fnn"  
commands.  
After the first packet is received into the first  
specified page, the TRI bit of the Status  
Register will be set to logic "1", causing an  
interrupt. Again, the interrupt need not be  
serviced immediately. Typically, the interrupt  
service routine will read the Status Register. At  
this point, the RI bit will be found to be a logic  
"1". After reading the Status Register, the  
"Clear Receive Interrupt" command should be  
issued, thus resetting the TRI bit and clearing  
the interrupt. Note that only the "Clear Receive  
Interrupt" command will clear the TRI bit and  
the interrupt. It is not necessary, however, to  
clear the bit or the interrupt right away because  
When the token is received again, the second  
transmission will be automatically initiated after  
the first is completed by using the stored  
"Enable Transmit from Page fnn" command.  
The operation is as if a new "Enable Transmit  
from Page fnn" command has just been issued.  
After the first Transmit status bits are cleared,  
38  
 
the status of the receive operation is double  
buffered in order to retain the results of the first  
reception for analysis by the processor,  
therefore the information will remain in the  
Status Register until the "Clear Receive  
Interrupt" command is issued. Note that the  
interrupt will remain active until the "Clear  
Receive Interrupt" command is issued, and the  
second interrupt will be stored until the first  
RESET DETAILS  
Internal Reset Logic  
The COM20020 includes special reset circuitry  
to guarantee smooth operation during reset.  
Special care is taken to assure proper operation  
in a variety of systems and modes of operation.  
The COM20020 contains digital filter circuitry  
and a Schmitt Trigger on the nRESET IN signal  
to reject glitches in order to ensure fault-free  
operation.  
interrupt is acknowledged.  
A minimum of  
200nS interrupt inactive time interval between  
interrupts is guaranteed.  
The second reception will occur as soon as a  
second packet is sent to the node, as long as  
the second "Enable Receive to Page fnn"  
command was issued. The operation is as if a  
new "Enable Receive to Page fnn" command  
has just been issued. After the first Receive  
status bits are cleared, the Status Register will  
again be updated with the results of the second  
reception and a second interrupt resulting from  
the second reception will occur.  
The COM20020 supports two reset options;  
software and hardware reset. A software reset  
is generated when a logic "1" is written to bit 7  
of the Configuration Register.  
remains in reset as long as this bit is set. The  
software reset does not affect the  
The device  
microcontroller interface modes determined  
after hardware reset, nor does it affect the  
contents of the Address Pointer Registers, the  
Configuration Register, or the Setup Register. A  
hardware reset occurs when a low signal is  
In the COM20020, the Receive Inhibit (RI) bit of  
the Interrupt Mask Register now masks only the  
TRI bit of the Status Register, not the RI bit as  
in the non-chaining mode. Since the TRI bit is  
only set upon reception of a packet (not by  
RESET), and since the TRI bit may easily be  
reset by issuing a "Clear Receive Interrupt"  
command, there is no need to use the RI bit of  
the Interrupt Mask Register to mask interrupts  
generated by the TRI bit of the Status Register.  
asserted on the nRESET IN input.  
The  
minimum reset pulse width is 3.2ms. This pulse  
width is used by the internal digital filter, which  
filters short glitches to allow only valid resets to  
occur.  
Upon reset, the transmitter portion of the device  
is disabled and the internal registers assume  
those states outlined in the Internal Registers  
section.  
In Command Chaining mode, the "Disable  
Receiver" command will cancel the oldest  
reception, unless the reception has already  
begun. If both receptions should be canceled,  
two "Disable Receiver" commands should be  
issued.  
After the nRESET IN signal is removed the user  
may write to the internal registers. Since writing  
a non-zero value to the Node ID Register wakes  
up the COM20020 core, the Setup Register  
should be written before the Node ID Register.  
Once the Node ID Register is written to, the  
COM20020 reads the value and executes two  
write cycles to the RAM buffer. Address 0 is  
written with the data D1H and address 1 is  
written with the Node ID. The data pattern D1H  
was chosen arbitrarily, and is meant to provide  
assurance of proper microsequencer operation.  
39  
 
node to join the network. Once the node joins  
the network, a reconfiguration occurs, as usual,  
thus setting the MYRECON bit of the Diagnostic  
Status Register.  
INITIALIZATION SEQUENCE  
Bus Determination  
The Tentative ID Register may be used to build  
a network map of all the nodes on the network,  
even once the COM20020 has joined the  
Writing to and reading from an odd address  
location from the COM20020's address space  
causes the COM20020 to determine the  
appropriate bus interface. When the COM20020  
is powered on the internal registers may be  
written to. Since writing a non-zero value to the  
Node ID Register wakes up the core, the Setup  
Register should be written to before the Node ID  
Register. Until a non-zero value is placed into  
the NID Register, no microcode is executed, no  
tokens are passed by this node, and no  
reconfigurations are generated by this node.  
Once a non-zero value is placed in the register,  
the core wakes up, but the node will not attempt  
to join the network until the TX Enable bit of the  
Configuration Register is set.  
network.  
Once a value is placed in the  
Tentative ID Register, the COM20020 looks for  
a response to a token whose DID matches the  
Tentative ID Register. The software can record  
this information and continue placing Tentative  
ID values into the register to continue building  
the network map. A complete network map is  
only valid until nodes are added to or deleted  
from the network. Note that a node cannot  
detect the existence of the next logical node on  
the network when using the Tentative ID. To  
determine the next logical node, the software  
should read the Next ID Register.  
IMPROVED DIAGNOSTICS  
Before setting the TX Enable bit, the software  
may make some determinations. The software  
may first observe the Receive Activity and the  
Token Seen bits of the Diagnostic Status  
Register to verify the health of the receiver and  
the network.  
The COM20020 allows the user to better  
manage the operation of the network through  
the use of the internal Diagnostic Status  
Register.  
Next, the uniqueness of the Node ID value  
placed in the Node ID Register is determined.  
The TX Enable bit should still be a logic "0" until  
it is ensured that the Node ID is unique. If this  
node ID already exists, the Duplicate ID bit of  
the Diagnostic Status Register is set after a  
maximum of 840mS (or 1680mS if the ET1 and  
ET2 bits are other than 1,1). To determine if  
another node on the network already has this ID,  
the COM20020 compares the value in the Node  
ID Register with the DID's of the token, and  
determines whether there is a response to it.  
Once the Diagnostic Status Register is read, the  
DUPID bit is cleared. The user may then  
attempt a new ID value, wait 840mS before  
checking the Duplicate ID bit, and repeat the  
process until a unique Node ID is found. At this  
point, the TX Enable bit may be set to allow the  
A
high level on the My Reconfiguration  
(MYRECON) bit indicates that the Token  
Reception Timer of this node expired, causing a  
reconfiguration by this node.  
Reconfiguration (RECON) bit of the Status  
Register interrupts the microcontroller, the  
interrupt service routine will typically read the  
MYRECON bit of the Diagnostic Status  
After the  
Register.  
Reading the Diagnostic Status  
Register resets the MYRECON bit. Successive  
occurrences of a logic "1" on the MYRECON bit  
indicates that a problem exists with this node.  
At that point, the transmitter should be disabled  
so that the entire network is not held down  
while the node is being evaluated.  
The Duplicate ID (DUPID) bit is used before the  
node joins the network to ensure that another  
40  
 
node with the same ID does not exist on the  
network. Once it is determined that the ID in the  
Node ID Register is unique, the software should  
write a logic "1" to bit 5 of the Configuration  
Register to enable the basic transmit function.  
This allows the node to join the network.  
incorrectly, there is noise on the network, or a  
reconfiguration is occurring.  
RCVACT=0, TOKEN=0, TXEN=1: No receive  
activity is seen and the basic transmit function  
is enabled. The transmitter and/or receiver are  
not functioning properly.  
The Receive Activity (RCVACT) bit of the  
Diagnostic Status Register will be set to a logic  
"1" whenever activity (logic "1") is detected on  
the RXIN pin.  
RCVACT=0, TOKEN=0, TXEN=0: No receive  
activity and basic transmit function disabled.  
This node is not connected to the network.  
The Token Seen (TOKEN) bit is set to a logic "1"  
whenever any token has been seen on the  
network (except those tokens transmitted by this  
node).  
The Excessive NAK (EXCNAK) bit is used to  
replace  
implemented in software.  
a
timeout function traditionally  
This function is  
necessary to limit the number of times a sender  
issues a FBE to a node with no available buffer.  
When the destination node replies to 128 FBEs  
with 128 NAKs or 4 FBEs with 4 NAKs, the  
EXCNAK bit of the sender is set, generating an  
The RCVACT and TOKEN bits may help the  
user to troubleshoot the network or the node. If  
unusual events are occurring on the network,  
the user may find it valuable to use the TXEN bit  
of the Configuration Register to qualify events.  
Different combinations of the RCVACT, TOKEN,  
and TXEN bits, as shown indicate different  
situations:  
interrupt.  
At this point the software may  
abandon the transmission via the "Disable  
Transmitter" command. This sets the TA bit to  
logic "1" when the node next receives the token,  
to allow a different transmission to occur. The  
timeout value for the EXNACK bit (128 or 4) is  
determined by the FOUR-NAKS bit on the Setup  
Register.  
Normal Results:  
RCVACT=1, TOKEN=1, TXEN=0: The node is  
The user may choose to wait for more NAK's  
before disabling the transmitter by taking  
advantage of the wraparound counter of the  
EXCNAK bit. When the EXCNAK bit goes high,  
indicating 128 or 4 NAKs, the "POR Clear  
Flags" command maybe issued to reset the bit  
so that it will go high again after another count  
of 128 or 4. The software may count the  
number of times the EXCNAK bit goes high, and  
once the final count is reached, the "Disable  
Transmitter" command may be issued.  
not part of the network.  
The network is  
operating properly without this node.  
RCVACT=1, TOKEN=1, TXEN=1: The node  
sees receive activity and sees the token. The  
basic transmit function is enabled. Network and  
node are operating properly.  
MYRECON=0, DUPID=0, RCVACT=1, TXEN=0,  
TOKEN=1: Single node network.  
Abnormal Results:  
The New Next ID bit permits the software to  
detect the withdrawal or addition of nodes to the  
network.  
RCVACT=1, TOKEN=0, TXEN=X: The node  
sees receive activity, but does not see the token.  
Either no other nodes exist on the network,  
some type of data corruption exists, the media  
driver is malfunctioning, the topology is set up  
The Tentative ID bit allows the user to build a  
network map of those nodes existing on the  
41  
 
network. This feature is useful because it  
minimizes the need for human intervention.  
When a value placed in the Tentative ID  
Register matches the Node ID of another node  
on the network, the TENTID bit is set, telling the  
software that this NODE ID already exists on the  
network. The software should periodically place  
values in the Tentative ID Register and monitor  
the New Next ID bit to maintain an updated  
network map.  
OSCILLATOR  
The COM20020 contains circuitry which, in  
conjunction with an external parallel resonant  
crystal or TTL clock, forms an oscillator.  
If an external crystal is used, two capacitors are  
needed (one from each leg of the crystal to  
ground). No external resistor is required, since  
the COM20020 contains an internal resistor.  
The crystal must have an accuracy of 0.020%  
or better.  
The XTAL2 side of the crystal may be loaded  
with a single 74HC-type buffer in order to  
generate a clock for other devices.  
The user may attach an external TTL clock,  
rather than a crystal, to the XTAL1 signal. In  
this case, a 390W pull-up resistor is required on  
XTAL1, while XTAL2 should be left  
unconnected.  
42  
 
OPERATIONAL DESCRIPTION  
MAXIMUM GUARANTEED RATINGS*  
Operating Temperature Range........................................................................................ 0oC to +70oC  
Storage Temperature Range...................................................................................... -55oC to +150oC  
Lead Temperature (soldering, 10 seconds) .............................................................................. +325 oC  
Positive Voltage on any pin, with respect to ground ...............................................................VDD+0.3V  
Negative Voltage on any pin, with respect to ground .................................................................... -0.3V  
Maximum VDD ............................................................................................................................... +7V  
*Stresses above those listed may cause permanent damage to the device. This is a stress rating only  
and functional operation of the device at these or any other condition above those indicated in the  
operational sections of this specification is not implied.  
NOTE: When powering this device from laboratory or system power supplies, it is important that the  
Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit  
voltage spikes or "glitches" on their outputs when the AC power is switched on or off. In addition,  
voltage transients on the AC power line may appear on the DC output. If this possibility exists it is  
suggested that a clamp circuit be used.  
DC ELECTRICAL CHARACTERISTICS  
VDD=5.0V±10%  
COM20020: TA=0oC to +70oC, COM20020I: TA=-40oC to +85oC  
PARAMETER  
SYMBOL  
MIN  
TYP  
MAX  
UNIT  
COMMENT  
TTL Levels  
Low Input Voltage 1  
(All inputs except A2,  
XTAL1, nRESET, nRD,  
nWR, and RXIN) High  
High Input Voltage 1  
(All inputs except A2,  
XTAL1, nRESET, nRD,  
nWR, and RXIN)  
VIL1  
0.8  
V
VIH1  
2.0  
V
TTL Levels  
Low Input Voltage 2  
(XTAL1)  
High Input Voltage 2  
(XTAL1)  
VIL2  
VIH2  
1.0  
V
V
TTL Clock Input  
4.0  
Low to High Threshold  
Input Voltage (A2,  
nRESET, nRD, nWR,  
RXIN)  
High to Low Threshold  
Input Voltage (A2,  
nRESET, nRD, nWR,  
RXIN)  
VILH  
1.8  
1.2  
V
Schmitt Trigger,  
All Values at VDD  
5V  
=
VIHL  
V
43  
 
PARAMETER  
SYMBOL  
MIN  
TYP  
MAX  
UNIT  
COMMENT  
ISINK=4mA  
Low Output Voltage 1  
(nPULSE1 in Normal  
Mode, nPULSE2,  
nTXEN)  
VOL1  
0.4  
V
High Output Voltage 1  
(nPULSE1 in Normal  
Mode, nPULSE2,  
nTXEN)  
VOH1  
2.4  
V
ISOURCE=-2mA  
Low Output Voltage 2  
(D0-D7)  
High Output Voltage 2  
(D0-D7)  
VOL2  
VOH2  
0.4  
0.8  
0.5  
V
V
ISINK=16mA  
2.4  
2.4  
ISOURCE=-12mA  
Low Output Voltage 3  
(nINTR)  
High Output Voltage 3  
(nINTR)  
VOL3  
VOH3  
V
V
ISINK=24mA  
ISOURCE=-10mA  
Low Output Voltage 4  
(nPULSE1 in Backplane  
Mode - Open Drain)  
VOL4  
V
ISINK=48mA  
Open Drain Driver  
Dynamic VDD Supply  
Current 1  
IDD1  
IP  
50  
mA  
Input Pull-up Current  
(nPULSE1 in Backplane  
Mode, A1, AD0-AD2,  
D3-D7)  
80  
200  
VIN=0.0V  
mA  
Input Leakage Current  
(All inputs except A1,  
AD0-AD2, D3-D7,  
XTAL1, XTAL2)  
IL  
±10  
VSS < VIN < VDD  
mA  
44  
 
CAPACITANCE (TA = 25°C; fC = 1MHz; VDD = 0V)  
Output and I/O pins capacitive load specified as follows:  
PARAMETER  
SYMBOL  
CIN  
MIN  
TYP  
MAX  
5.0  
UNIT  
pF  
COMMENT  
Input Capacitance  
Output Capacitance 1  
(All outputs except  
nPULSE1 in BackPlane  
Mode)  
Output Capacitance 2  
(nPULSE1, in  
COUT1  
45  
pF  
Maximum  
Capacitive Load  
which can be  
supported by each  
output.  
COUT2  
400  
pF  
BackPlane  
Mode Only - Open  
Drain)  
AC Measurements are taken at the following points:  
Inputs:  
Outputs:  
t
t
2.0V  
2.4V  
1.4V  
0.4V  
50%  
50%  
0.8V  
2.0V  
0.8V  
t
2.4V  
1.4V  
0.4V  
t
Inputs are driven at 2.4V for logic "1" and 0.4 V for logic "0".  
Outputs are measured at 2.0V min. for logic "1" and 0.8V max. for logic "0".  
45  
 
TIMING DIAGRAMS  
AD0-AD2,  
D3-D7  
VALID  
t3  
VALID DATA  
t1  
t2,  
t4  
nCS  
ALE  
nDS  
t6  
t7  
t5  
t8  
t9  
t10  
DIR  
Parameter  
min  
max  
units  
t1 Address Setup to ALE Low  
t2 Address Hold from ALE Low  
t3 nCS Setup to ALE Low  
t4 nCS Hold from ALE Low  
t5 ALE Low to nDS Low  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
30  
10  
10  
20  
15  
40  
20  
t6 nDS Low to Valid Data  
0
4T*  
10  
t7 nDS High to Data High Impedance  
t8 Cycle Time (nDS Low to Next Time Low)  
t9 DIR Setup to nDS Active  
t10 DIR Hold from nDS Inactive  
10  
*
T is the Arbitration Clock Period.  
T is identical to XTAL1 if SLOW ARB = 0,  
T is twice XTAL1 period if SLOW ARB = 1  
Note 1:  
The Microcontroller typically accesses the COM20020 on every other cycle.  
Therefore, the cycle time specified in the microcontroller's datasheet  
should be doubled when considering back-to-back COM20020 cycles.  
FIGURE 10 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE  
46  
 
AD0-AD2,  
D3-D7  
VALID  
VALID DATA  
t1  
t2,  
t4  
nCS  
t3  
ALE  
nRD  
t6  
t7  
t5  
t8  
Parameter  
max  
units  
min  
t1  
t2  
t3  
Address Setup to ALE Low  
Address Hold from ALE Low  
nCS Setup to ALE Low  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
30  
10  
10  
20  
15  
t4 nCS Hold from ALE Low  
t5  
t6  
t7 nRD High to Data High Impedance  
t8 Cycle Time (nRD Low to Next Time Low)  
ALE Low to nRD Low  
nRD Low to Valid Data  
40  
20  
0
4T*  
*
T is the Arbitration Clock Period.  
T is identical to XTAL1 if SLOW ARB = 0,  
T is twice XTAL1 period if SLOW ARB = 1  
Note 1:  
The Microcontroller typically accesses the COM20020 on every other cycle.  
Therefore, the cycle time specified in the microcontroller's datasheet  
should be doubled when considering back-to-back COM20020 cycles.  
FIGURE 10A - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE  
47  
 
AD0-AD2,  
D3-D7  
VALID  
VALID DATA  
t1  
t2,  
t4  
nCS  
t3  
ALE  
nDS  
t7  
t5  
t6  
Note 2  
t8**  
t8  
DIR  
t10  
t9  
Parameter  
min  
max  
units  
Address Setup to ALE Low  
Address Hold from ALE Low  
nCS Setup to ALE Low  
nCS Hold from ALE Low  
ALE Low to nDS Low  
Valid Data Setup to nDS High  
Data Hold from nDS High  
Cycle Time (nDS Low to Next Time Low)**  
DIR Setup to nDS Active  
t1  
t2  
t3  
t4  
t5  
t6  
t7  
t8  
t9  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
30  
10  
10  
20  
15  
30  
10  
4T*  
10  
10  
DIR Hold from nDS Inactive  
t10  
* T is the Arbitration Clock Period.  
T is identical to XTAL1 if SLOW ARB = 0,  
T is twice XTAL1 period if SLOW ARB = 1  
The Microcontroller typically accesses the COM20020 on every other cycle.  
Therefore, the cycle time specified in the microcontroller's datasheet  
Note 1:  
should be doubled when considering back-to-back COM20020 cycles.  
**  
Any cycle occurring after a write to Address Pointer Low Register requires a  
minimum of 4T from the trailing edge of nDS to the leading edge of the  
next nDS.  
Note 2:  
FIGURE 11 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE  
48  
 
AD0-AD2,  
D3-D7  
VALID  
t3  
VALID DATA  
t1  
t2,  
t4  
nCS  
ALE  
t7  
t5  
nWR  
t6  
Note 2  
t8**  
t8  
min  
Parameter  
max  
units  
Address Setup to ALE Low  
Address Hold from ALE Low  
nCS Setup to ALE Low  
nCS Hold from ALE Low  
ALE Low to nWR Low  
Valid Data Setup to nWR High  
Data Hold from nWR High  
Cycle Time (nWR Low to Next Time Low)**  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
t1  
30  
10  
10  
20  
15  
30  
10  
t2  
t3  
t4  
t5  
t6  
t7  
t8  
4T*  
*
T is the Arbitration Clock Period.  
T is identical to XTAL1 if SLOW ARB = 0,  
T is twice XTAL1 period if SLOW ARB = 1  
The Microcontroller typically accesses the COM20020 on every other cycle.  
Therefore, the cycle time specified in the microcontroller's datasheet  
should be doubled when considering back-to-back COM20020 cycles.  
Note 1:  
**  
Any cycle occurring after a write to Address Pointer Low Register requires a  
minimum of 4T from the trailing edge of nWR to the leading edge of the  
next nWR.  
Note 2:  
FIGURE 11A - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE  
49  
 
A0-A2  
nCS  
VALID  
t1  
t2  
t4  
t3  
t5  
nRD  
t7  
t6  
D0-D7  
VALID DATA  
Parameter  
min  
max  
units  
Address Setup to nRD Active  
t1  
15  
nS  
nS  
nS  
nS  
nS  
nS  
t2  
t3  
t4  
t5  
t6  
10  
5**  
0
Address Hold from nRD Inactive  
nCS Setup to nRD Active  
nCS Hold from nRD Inactive  
Cycle Time (nRD Low to Next Time Low)  
nRD Low to Valid Data  
nRD High to Data High Impedance  
4T*  
40  
20  
t7  
0
nS  
*
T is the Arbitration Clock Period.  
T is identical to XTAL1 if SLOW ARB = 0,  
T is twice XTAL1 period if SLOW ARB = 1  
nCS may become active after control becomes active, but the access time  
**  
will now be 45nS measured from the leading edge of nCS.  
The Microcontroller typically accesses the COM20020 on every other cycle.  
Note 1:  
Therefore, the cycle time specified in the microcontroller's datasheet  
should be doubled when considering back-to-back COM20020 cycles.  
FIGURE 12 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE  
50  
 
A0-A2  
nCS  
VALID  
t1  
t2  
t4  
t7  
t3  
t5  
DIR  
t6  
nDS  
t8  
t9  
D0-D7  
VALID DATA  
min  
Parameter  
t1 Address Setup to nDS Active  
t2 Address Hold from nDS Inactive  
t3 nCS Setup to DS Active  
t4 nCS Hold from DS Inactive  
t5 DIR Setup to nDS Active  
max  
units  
15  
10  
5**  
0
10  
nS  
nS  
nS  
nS  
nS  
t6  
t7  
t8  
t9  
Cycle Time (nDS Low to Next Time Low)  
DIR Hold from nDS Active  
nDS Low to Valid Data  
4T*  
10  
nS  
nS  
nS  
nS  
40  
20  
nDS High to Data High Impedence  
0
*
T is the Arbitration Clock Period.  
T is identical to XTAL1 if SLOW ARB = 0,  
T is twice XTAL1 period if SLOW ARB = 1  
**  
nCS may become active after control becomes active, but the access time will  
now be 45nS measured from the leading edge of nCS.  
The Microcontroller typically accesses the COM20020 on every other cycle.  
Note 1:  
Therefore, the cycle time specified in the microcontroller's datasheet  
should be doubled when considering back-to-back COM20020 cycles.  
FIGURE 12A - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE  
51  
 
A0-A2  
nCS  
VALID  
t1  
t2  
t4  
t3  
t5  
nWR  
Note 2  
t5**  
t6  
t7  
D0-D7  
VALID DATA  
Parameter  
min  
max units  
t1  
Address Setup to nWR Active  
15  
nS  
t2  
t3  
Address Hold from nWR Inactive  
nCS Setup to WR Active  
10  
5
nS  
nS  
0
nCS Hold from nWR Inactive  
t4  
t5  
t6  
t7  
nS  
nS  
nS  
nS  
Cycle Time (nWR Low to Next Time Low)**  
Valid Data Setup to nWR High  
Data Hold from nWR High  
4T*  
30**  
10  
*
T is the Arbitration Clock Period.  
T is identical to XTAL1 if SLOW ARB = 0,  
T is twice XTAL1 period if SLOW ARB = 1  
**nCS may become active after control becomes active, but the data setup time will now  
be 30 nS measured from the later of nCS falling or Valid Data available.  
Note 1: The Microcontroller typically accesses the COM20020 on every other cycle.  
Therefore, the cycle time specified in the microcontroller's datasheet  
should be doubled when considering back-to-back COM20020 cycles.  
Note 2:  
Any cycle occurring after a write to the Address Pointer Low Register  
requires a minimum of 4T from the trailing edge of nWR to the leading edge  
of the next nWR.  
FIGURE 13 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE  
52  
 
A0-A2  
nCS  
VALID  
t1  
t2  
t7  
t4  
t3  
t5  
DIR  
t6  
nDS  
Note 2  
t6**  
t8  
t9  
D0-D7  
VALID DATA  
Parameter  
min  
15  
10  
5
max  
units  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
t1 Address Setup to nDS Active  
t2 Address Hold from nDS Inactive  
t3 nCS Setup to nDS Active  
t4 nCS Hold from nDS Inactive  
t5 DIR Setup to nDS Active  
t6 Cycle Time (nDS Low to Next Time Low)**  
t7 DIR Hold from nDS Inactive  
t8 Valid Data Setup to nDS High  
t9 Data Hold from nDS High  
0
10  
4T*  
10  
30**  
10  
*
T is the Arbitration Clock Period.  
T is identical to XTAL1 if SLOW ARB = 0,  
T is twice XTAL1 period if SLOW ARB = 1  
**nCS may become active after control becomes active, but the data setup time will  
now be 30 nS measured from the later of nCS falling or Valid Data available.  
Note 1: The Microcontroller typically accesses the COM20020 on every other cycle.  
Therefore, the cycle time specified in the microcontroller's datasheet  
should be doubled when considering back-to-back COM20020 cycles.  
Note 2:  
Any cycle occurring after a write to the Address Pointer Low Register  
requires a minimum of 4T from the trailing edge of nDS to the leading  
edge of the next nDS.  
FIGURE 13A - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE  
53  
 
nTXEN  
t4  
t5  
t2  
t1  
nPULSE1  
LAST BIT  
(400 nS BIT TIME)  
t3  
t2  
t1  
nPULSE2  
RXIN  
t6  
t7  
Parameter  
min  
typ  
100 *  
max units  
nS  
nS  
+10 nS  
950 nS  
350 nS  
t1  
t2  
t3  
t4  
t5  
nPULSE1, nPULSE2 Pulse Width  
nPULSE1, nPULSE2 Period  
nPULSE1, nPULSE2 Overlap  
nTXEN Low to nPULSE1 Low**  
*
400  
0
-10  
850  
250  
Beginning of Last Bit Time to nTXEN High**  
*
t6  
t7  
nS  
nS  
RXIN Pulse Width  
RXIN Period  
100  
10  
400 *  
* t1 = 2 x (crystal period) for clock frequencies other than 20 MHz.  
* t2,t7 = 8 x (crystal period) for clock frequencies other than 20 MHz.  
This period applies to data of two consecutive one's.  
** t4: For clock frequencies other than 20 MHz, t4 = 18 x (crystal period)  
+ 50 nsec.  
** t5: For clock frequencies other than 20 MHz, t5 = 6 x (crystal period)  
+ 50 nsec.  
FIGURE 14 - NORMAL MODE TRANSMIT OR RECEIVE TIMING  
(These signals are to and from the hybrid)  
54  
 
nTXEN  
t1  
t3  
t2  
nPULSE1  
t9  
t8  
LAST BIT  
t4  
(400 nS BIT TIME)  
t5  
t6  
nPULSE2  
(Internal Clk)  
t7  
t10  
RXIN  
t11  
Parameter  
min typ max units  
0
50  
nPULSE2 High to nTXEN Low  
t1  
t2  
t3  
t4  
t5  
t6  
t7  
t8  
nS  
nPULSE1 Pulse Width  
nPULSE1 Period  
nPULSE2 Low to nPULSE1 Low  
nPULSE2 High Time  
nPULSE2 Low Time  
nPULSE2 Period  
200*  
400*  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
-25  
25  
100*  
100*  
200*  
50  
0
nPULSE2 High to nTXEN High  
(First rising edge on nPULSE2 after Last Bit Time)  
nTXEN Low to first nPULSE1 Low**  
650  
10  
750  
t9  
nS  
t10  
t11  
RXIN Pulse Width  
RXIN Period  
200*  
400*  
nS  
nS  
* t5,t6 = 2 x (crystal period) for clock frequencies other than 20 MHz.  
* t2,t7,t10 = 4 x (crystal period) for clock frequencies other than 20 MHz.  
* t3,t11 = 8 x (crystal period) for clock frequencies other than 20 MHz.  
This period applies to data of two consecutive one's.  
** t9: For clock frequencies other than 20 MHz, t9 = 14 x (clock period) + 50 nsec.  
FIGURE 15 - BACKPLANE MODE TRANSMIT OR RECEIVE TIMING  
(These signals are to and from the differential driver or the cable)  
55  
 
t1  
t2  
t3  
XTAL1  
Parameter  
min  
typ  
max units  
nS  
nS  
nS  
t1  
t2  
t3  
t4  
Input Clock High Time  
Input Clock Low Time  
Input Clock Period  
20  
20  
50  
10  
100  
20  
Input Clock Frequency  
MHz  
FIGURE 16 - TTL INPUT TIMING ON XTAL1 PIN  
t1  
nRESET IN  
nINTR  
t2  
Parameter  
min  
typ  
max units  
t1  
t2  
nRESET IN Pulse Width  
nINTR High to Next nINTR Low  
µS  
nS  
3.2  
200  
FIGURE 17 - RESET AND INTERRUPT TIMING  
56  
 
G
PIN NO.  
1
E
J
A
F
B
B1  
D3  
D2  
R
J
C
J
D1  
D
A1  
DIM  
28L  
.160-.180  
A
.090-.120  
.013-.021  
.026-.032  
A1  
B
B1  
.020-.045  
.485-.495  
.450-.456  
.390-.430  
.300 REF  
C
D
D1  
D2  
D3  
E
F
G
J
.050 BSC  
.042-.056  
.042-.048  
.000-.020  
.025-.045  
R
NOTES:  
1.  
All dimensions are in inches.  
2. Circle indicating pin 1 can appear on a top surface as shown on the drawing or  
right above it on a beveled edge.  
FIGURE 18 - 28-PIN PLCC PACKAGE DIMENSIONS  
57  
 
E1  
E
C
e
A
D
e
B
A2  
Base  
Plane  
A
A1  
Seating  
Plane  
L
e
B
B1  
S
DIM  
A
A1  
A2  
B
B1  
C
D
E
E1  
e
eA  
eB  
L
24L  
.090-.150  
.020-.065  
.145-.155  
.016-.021  
.060-.070  
.010-.014  
1.245-1.265  
.590-.630  
.530-.545  
.100BSC  
.600REF  
.610-.670  
.120-.140  
.065-.085  
S
Note: All dimensions are in inches.  
FIGURE 18A - 24-PIN DIP PACKAGE DIMENSIONS  
58  
 
COM20020 ERRATA SHEET  
DATE  
REVISED  
PAGE  
5
SECTION/FIGURE/ENTRY  
CORRECTION  
See Italicized Text  
See Italicized Text  
See Italicized Text  
See Italicized Text  
See Italicized Text  
See Italicized Text  
See Italicized Text  
See Italicized Text  
See Italicized Text  
See Italicized Text  
See Italicized Text  
See Italicized Text  
Bits 4,3 - See Italicized Text  
Pin No. 18/DESCRIPTION  
Network Protocol  
5/29/96  
5/29/96  
5/29/96  
5/29/96  
5/29/96  
5/29/96  
5/29/96  
5/29/96  
5/29/96  
5/29/96  
5/29/96  
5/29/96  
5/29/96  
5/29/96  
8
9
Network Reconfiguration  
Extended Timeout Function  
Line Protocol  
9
10  
12  
15  
17  
22  
23  
23  
24  
29  
30  
Microcontroller Interface  
Backplane Configuration  
Programmable TXEN Polarity  
Data Register  
Status Register  
Address Pointer Registers  
Configuration Register  
Table 9  
Table 10  
Bit 5 and Bits 3,2,1 - See Italicized  
Text  
35  
40  
42  
Transmit Sequence  
Bus Determination  
Abnormal Results  
See Italicized Text  
See Italicized Text  
See Italicized Text  
5/29/96  
5/29/96  
5/29/96  
59  
 
STANDARD MICROSYSTEMS CORP.  
Circuit diagrams utilizing SMSC products are included as a means of illustrating  
typical applications; consequently complete information sufficient for  
construction purposes is not necessarily given. The information has been  
carefully checked and is believed to be entirely reliable. However, no  
responsibility is assumed for inaccuracies. Furthermore, such information does  
not convey to the purchaser of the semiconductor devices described any  
licenses under the patent rights of SMSC or others. SMSC reserves the right to  
make changes at any time in order to improve design and supply the best  
product possible. SMSC products are not designed, intended, authorized or  
warranted for use in any life support or other application where product failure  
could cause or contribute to personal injury or severe property damage. Any  
and all such uses without prior written approval of an Officer of SMSC and  
further testing and/or modification will be fully at the risk of the customer.  
COM20020 Rev. 5/29/96  
 

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