SMSC Network Card USB3250 User Manual

USB3250  
Hi-Speed USB Device  
Transceiver with UTMI  
Interface  
Data Brief  
PRODUCT FEATURES  
USB-IF "Hi-Speed" certified to USB 2.0 electrical  
specification  
Applications  
The Universal Serial Bus (USB) is the preferred  
interface to connect Hi-Speed PC peripherals.  
Interface compliant with the UTMI specification  
(60MHz 8-bit unidirectional interface or 30MHz 16-bit  
bidirectional interface)  
Digital Still and Video Cameras  
MP3 Players  
Supports 480Mbps High Speed (HS) and 12Mbps  
Full Speed (FS) serial data transmission rates  
External Hard Drives  
Scanners  
Integrated 45Ω and 1.5kΩ termination resistors  
reduce external component count  
Entertainment Devices  
Printers  
Internal short circuit protection of DP and DM lines  
On-chip oscillator operates with low cost 12MHz  
crystal  
Test and Measurement Systems  
POS Terminals  
Robust and low power digital clock and data recovery  
circuit  
Set Top Boxes  
SYNC and EOP generation on transmit packets and  
detection on receive packets  
NRZI encoding and decoding  
Bit stuffing and unstuffing with error detection  
Supports the USB suspend state, HS detection, HS  
Chirp, Reset and Resume  
Support for all test modes defined in the USB 2.0  
specification  
Draws 72mA (185mW) maximum current  
consumption in HS mode - ideal for bus powered  
functions  
On-die decoupling capacitance and isolation for  
immunity to digital switching noise  
Available in a 56-pin QFN package  
Full industrial operating temperature range from  
o
o
-40 C to +85 C (ambient)  
SMSC USB3250  
PRODUCT PREVIEW  
Revision 1.7 (05-11-07)  
 
Hi-Speed USB Device Transceiver with UTMI Interface  
General Description  
The USB3250 provides the Physical Layer (PHY) interface to a USB 2.0 Device Controller. The IC is  
available in a 56 pin QFN.  
The USB3250 is a USB 2.0 physical layer transceiver (PHY) integrated circuit. SMSC's proprietary  
technology results in low power dissipation, which is ideal for building a bus powered USB 2.0  
peripheral. The PHY can be configured for either an 8-bit unidirectional or a 16-bit bidirectional parallel  
interface, which complies with the USB Transceiver Macrocell Interface (UTMI) specification. It  
supports 480Mbps transfer rate, while remaining backward compatible with USB 1.1 legacy protocol  
at 12Mbps.  
All required termination for the USB 2.0 Transceiver is internal. Internal 5.25V short circuit protection  
of DP and DM lines is provided for USB compliance.  
While transmitting data, the PHY serializes data and generates SYNC and EOP fields. It also performs  
needed bit stuffing and NRZI encoding. Likewise, while receiving data, the PHY de-serializes incoming  
data, stripping SYNC and EOP fields and performs bit un-stuffing and NRZI decoding.  
Block Diagram  
PWR  
CONTROL  
System  
Clocking  
PLL and  
XTAL OSC  
TX  
LOGIC  
TX  
RPU_EN  
1.5kΩ  
TX State  
Machine  
VPO  
VMO  
OEB  
Parallel to  
Serial  
FS  
TX  
DATABUS16_8  
RESET  
Conversion  
HS_DATA  
Bit Stuff  
SUSPENDN  
XCVRSELECT  
TERMSELECT  
OPMODE[1:0]  
HS_DRIVE_ENABLE  
HS_CS_ENABLE  
HS  
TX  
NRZ  
Encode  
DP  
DM  
RX  
LINESTATE[1:0]  
CLKOUT  
RX  
LOGIC  
FS  
SE+  
DATA[15:0] *  
RX State  
Machine  
VP  
VM  
TXVALID  
TXREADY  
VALIDH  
FS  
SE-  
Serial to  
Parallel  
Conversion  
Clock  
Recovery Unit  
FS  
RX  
Clock  
and  
Data  
Bit Unstuff  
RXVALID  
NRZI  
Decode  
Recovery  
RXACTIVE  
RXERROR  
HS  
RX  
Elasticity  
Buffer  
BIASING  
HS  
SQ  
Bandgap Voltage Reference  
Current Reference  
Figure 1 USB3250 Functional Block Diagram  
SMSC USB3250  
3
Revision 1.7 (05-11-07)  
PRODUCT PREVIEW  
 
Hi-Speed USB Device Transceiver with UTMI Interface  
Pin Configuration  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
DATA[1]  
DATA[2]  
DATA[3]  
DATA[4]  
VDD1.8  
DATA[5]  
DATA[6]  
DATA[7]  
DATA[8]  
VSS  
VSSA  
DM  
1
2
DP  
3
VDDA3.3  
VSSA  
4
USB 2.0  
USB3250  
PHY IC  
5
RBIAS  
VDDA3.3  
VSSA  
6
7
8
VSSA  
9
XI  
10  
11  
12  
13  
14  
DATA[9]  
DATA[10]  
DATA[11]  
DATA[12]  
XO  
VDDA1.8  
SUSPENDN  
VSS  
Figure 2 56-Pin USB3250 Pin Configuration (Top View)  
Revision 1.7 (05-11-07)  
4
SMSC USB3250  
PRODUCT PREVIEW  
 
Hi-Speed USB Device Transceiver with UTMI Interface  
Pin Description Tables  
Table 1 System Interface Pins  
ACTIVE  
LEVEL  
NAME  
RESET  
DIRECTION  
DESCRIPTION  
Input  
High  
Reset. Reset all state machines. After coming out of reset, must  
wait 5 rising edges of clock before asserting TXValid for transmit.  
Assertion of Reset: May be asynchronous to CLKOUT.  
De-assertion of Reset: Must be synchronous to CLKOUT unless  
RESET is asserted longer than two periods of CLKOUT.  
XCVRSELECT  
TERMSELECT  
SUSPENDN  
Input  
Input  
Input  
N/A  
N/A  
Low  
Transceiver Select. This signal selects between the FS and HS  
transceivers:  
0: HS transceiver enabled  
1: FS transceiver enabled.  
Termination Select. This signal selects between the FS and HS  
terminations:  
0: HS termination enabled  
1: FS termination enabled  
Suspend. Places the transceiver in a mode that draws minimal  
power from supplies. Shuts down all blocks not necessary for  
Suspend/Resume operation. While suspended, TERMSELECT  
must always be in FS mode to ensure that the 1.5k Ω pull-up on  
DP remains powered.  
0: Transceiver circuitry drawing suspend current  
1: Transceiver circuitry drawing normal current  
CLKOUT  
Output  
Input  
Rising Edge System Clock. This output is used for clocking receive and  
transmit parallel data at 60MHz (8-bit mode) or 30MHz (16-bit  
mode). When in 8-bit mode, this specification refers to CLKOUT  
as CLK60. When in 16-bit mode, CLKOUT is referred to as  
CLK30.  
OPMODE[1:0]  
N/A  
Operational Mode. These signals select between the various  
operational modes:  
[1] [0] Description  
0
0
1
1
0
1
0
1
0: Normal Operation  
1: Non-driving (all terminations removed)  
2: Disable bit stuffing and NRZI encoding  
3: Reserved  
LINESTATE[1:0]  
Output  
N/A  
Line State. These signals reflect the current state of the USB  
data bus in FS mode, with [0] reflecting the state of DP and [1]  
reflecting the state of DM. When the device is suspended or  
resuming from a suspended state, the signals are combinatorial.  
Otherwise, the signals are synchronized to CLKOUT.  
[1] [0] Description  
0
0
1
1
0
1
0
1
0: SE0  
1: J State  
2: K State  
3: SE1  
DATABUS16_8  
Input  
N/A  
Databus Select. Selects between 8-bit and 16-bit data transfers.  
0: 8-bit data path enabled. VALIDH is undefined. CLKOUT =  
60MHz.  
1: 16-bit data path enabled. CLKOUT = 30MHz.  
SMSC USB3250  
5
Revision 1.7 (05-11-07)  
PRODUCT PREVIEW  
 
Hi-Speed USB Device Transceiver with UTMI Interface  
Table 2 Data Interface Pins  
ACTIVE  
LEVEL  
NAME  
DIRECTION  
DESCRIPTION  
DATA[15:0]  
Bidir  
N/A  
DATA BUS. 16-BIT BIDIRECTIONAL MODE.  
TXVALID  
RXVALID  
VALIDH  
DATA[15:0]  
Not used  
0
0
0
1
X
0
DATA[7:0] output is valid  
for receive  
VALIDH is an output  
0
1
1
1
X
X
1
0
1
DATA[15:0] output is  
valid for receive  
VALIDH is an output  
DATA[7:0] input is valid  
for transmit  
VALIDH is an input  
DATA[15:0] input is valid  
for transmit  
VALIDH is an input  
DATA BUS. 8-BIT UNIDIRECTIONAL MODE.  
TXVALID RXVALID DATA[15:0]  
0
0
1
0
1
Not used  
DATA[15:8] output is valid for receive  
DATA[7:0] input is valid for transmit  
X
TXVALID  
Input  
High  
Transmit Valid. Indicates that the TXDATA bus is valid for  
transmit. The assertion of TXVALID initiates the transmission of  
SYNC on the USB bus. The negation of TXVALID initiates EOP  
on the USB.  
Control inputs (OPMODE[1:0], TERMSELECT,XCVRSELECT)  
must not be changed on the de-assertion or assertion of TXVALID.  
The PHY must be in a quiescent state when these inputs are  
changed.  
TXREADY  
VALIDH  
Output  
Bidir  
High  
N/A  
Transmit Data Ready. If TXVALID is asserted, the SIE must  
always have data available for clocking into the TX Holding  
Register on the rising edge of CLKOUT. TXREADY is an  
acknowledgement to the SIE that the transceiver has clocked the  
data from the bus and is ready for the next transfer on the bus. If  
TXVALID is negated, TXREADY can be ignored by the SIE.  
Transmit/Receive High Data Bit Valid (used in 16-bit mode  
only). When TXVALID = 1, the 16-bit data bus direction is  
changed to inputs, and VALIDH is an input. If VALIDH is asserted,  
DATA[15:0] is valid for transmission. If deasserted, only DATA[7:0]  
is valid for transmission. The DATA bus is driven by the SIE.  
When TXVALID = 0 and RXVALID = 1, the 16-bit data bus  
direction is changed to outputs, and VALIDH is an output. If  
VALIDH is asserted, the DATA[15:0] outputs are valid for receive.  
If deasserted, only DATA[7:0] is valid for receive. The DATA bus  
is read by the SIE.  
RXVALID  
Output  
High  
Receive Data Valid. Indicates that the RXDATA bus has received  
valid data. The Receive Data Holding Register is full and ready to  
be unloaded. The SIE is expected to latch the RXDATA bus on the  
rising edge of CLKOUT.  
RXACTIVE  
RXERROR  
Output  
Output  
High  
High  
Receive Active. Indicates that the receive state machine has  
detected Start of Packet and is active.  
Receive Error. 0: Indicates no error. 1: Indicates a receive error  
has been detected. This output is clocked with the same timing as  
the RXDATA lines and can occur at anytime during a transfer.  
Revision 1.7 (05-11-07)  
6
SMSC USB3250  
PRODUCT PREVIEW  
 
Hi-Speed USB Device Transceiver with UTMI Interface  
Table 3 USB I/O Pins  
ACTIVE  
LEVEL  
NAME  
DIRECTION  
DESCRIPTION  
DP  
I/O  
I/O  
N/A  
N/A  
USB Positive Data Pin.  
DM  
USB Negative Data Pin.  
Table 4 Biasing and Clock Oscillator Pins  
ACTIVE  
NAME  
DIRECTION  
LEVEL  
DESCRIPTION  
RBIAS  
Input  
N/A  
External 1% bias resistor. Requires a 12KΩ resistor to ground.  
Used for setting HS transmit current level and on-chip termination  
impedance.  
XI/XO  
Input  
N/A  
External crystal. 12MHz crystal connected from XI to XO.  
Table 5 Power and Ground Pins  
ACTIVE  
NAME  
DIRECTION  
LEVEL  
DESCRIPTION  
VDD3.3  
VDD1.8  
VSS  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
3.3V Digital Supply. Powers digital pads. See Note 2.1  
1.8V Digital Supply. Powers digital core.  
Digital Ground. See Note 2.2  
VDDA3.3  
3.3V Analog Supply. Powers analog I/O and 3.3V analog  
circuitry.  
VDDA1.8  
VSSA  
N/A  
N/A  
N/A  
N/A  
1.8V Analog Supply. Powers 1.8V analog circuitry. See Note 2.1  
Analog Ground. See Note 2.2  
Note 2.1 A Ferrite Bead (with DC resistance <.5 Ohms) is recommended for filtering between both  
the VDD3.3 and VDDA3.3 supplies and the VDD1.8 and VDDA1.8 Supplies.  
Note 2.2 All VSS and VSSA are bonded to the exposed pad under the IC in the package. The  
exposed pad must be connected to solid GND plane on printed circuit board.  
SMSC USB3250  
7
Revision 1.7 (05-11-07)  
PRODUCT PREVIEW  
 
   
Hi-Speed USB Device Transceiver with UTMI Interface  
Application Diagram  
VDD3.3  
10uF  
VDD1.8  
1uF  
Voltage  
Regulator  
UTMI  
45  
51  
50  
46  
52  
47  
54  
TXVALID  
TXREADY  
RXACTIVE  
RXVALID  
RXERROR  
VALIDH  
1uF  
10uF  
44  
42  
41  
40  
39  
37  
36  
35  
DATA 0  
DATA 1  
DATA 2  
DATA 3  
DATA 4  
DATA 5  
DATA 6  
DATA 7  
DATABUS16_8  
17  
18  
XCVRSELECT  
TERMSELECT  
34  
32  
31  
30  
29  
27  
26  
25  
13  
24  
DATA 8  
DATA 9  
SUSPENDN  
RESET  
DATA 10  
DATA 11  
DATA 12  
DATA 13  
DATA 14  
DATA 15  
20  
19  
OPMODE 0  
OPMODE 1  
22  
21  
LINESTATE 0  
LINESTATE 1  
49  
6
CLKOUT  
USB  
RBIAS  
DP  
C LOAD  
12KΩ  
10  
3
2
XI  
12MHz  
Crystal  
1ΜΩ  
USB-B  
11  
XO  
DM  
C LOAD  
POWER  
1
5
8
9
VSSA  
VSSA  
VSSA  
VSSA  
12  
VDDA1.8  
Ferrite Bead  
16  
23  
38  
53  
VDD1.8  
VDD1.8  
VDD1.8  
VDD1.8  
10uF  
VDD1.8  
14  
33  
48  
55  
56  
VSS  
VSS  
VSS  
VSS  
VSS  
4
7
VDDA3.3  
VDDA3.3  
Ferrite Bead  
15  
28  
43  
VDD3.3  
VDD3.3  
VDD3.3  
VDD3.3  
GND  
Figure 3 Application Diagram for 56-pin QFN Package  
Revision 1.7 (05-11-07)  
8
SMSC USB3250  
PRODUCT PREVIEW  
 
Package Outline  
REVISION HISTORY  
DESCRIPTION  
REVISION  
DATE  
2/07/04  
10/7/04  
7/2/05  
RELEASED BY  
S.K.ILIEV  
D
D2  
A
B
C
INITIAL RELEASE  
D1  
e
TERMINAL #1  
IDENTIFIER AREA  
REMO VE "PRELIMINARY" NOTE  
S.K.ILIEV  
3
L(MAX) FROM 0.55 TO 0.50. ADDED D2/E2 VARIATIONS TABLE  
S.K.ILIEV  
(D/2  
X
E/2)  
3
TERMINAL #1  
IDENTIFIER AREA  
(D1/2 X E1/2)  
E1  
E
E2  
2
EXPOSED PAD  
56X  
L
2
56X  
b
4X 45°X0.6 MAX (OPTIONAL)  
TOP VIEW  
BOTTOM VIEW  
A2  
A
A1  
SIDE VIEW  
D2 / E2 VARIATIONS  
CATALOG PART  
N O TES:  
1. ALL DIMENSIONS ARE IN MILLIM ETER.  
2. POSITION TOLERANCE OF EACH TERMINAL AND EXPOSED PAD IS ± 0.05mm AT MAXIMUM MATERIAL  
CONDITION. DIMENSIONS "b" APPLIES TO PLATED TERMINALS AND IT IS MEASURED BETWEEN 0.15 AND  
0.30 m m FROM THE TERM INAL TIP.  
3. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED W ITHIN THE AREA INDICATED.  
THIRD ANGLE PROJECTION  
UNLESS O THERW ISE SPECIFIED  
DIM ENSIONS ARE IN MILLIMETERS  
AND TOLERANCES ARE:  
80 ARKAY DRIVE  
HAUPPAUG E, NY 11788  
DECIMAL  
ANG ULAR  
±1°  
USA  
X.X  
±0.1  
±0.05  
X.XX  
X.XXX ±0.025  
TITLE  
NAME  
DATE  
DIM AND TO L PER ASM E Y14.5M  
MATERIAL  
-
1994  
PACKAGE OUTLINE  
56 TERMINAL QFN, 8x8mm BODY, 0.5mm PITCH  
DRAWN  
-
S.K.ILIEV  
2/06/04  
3-D VIEWS  
REV  
FIN ISH  
C HECKED  
DWG NUMBER  
-
S.K.ILIEV  
2/07/04  
2/07/04  
C
MO-56-QFN-8x8  
APPR OVED  
SCALE  
STD COMPLIANCE  
SHEET  
PRINT W ITH "SCALE TO FIT"  
DO NO T SCALE DRAWING  
S.K.ILIEV  
1:1  
JEDEC: MO-220  
1 OF 1  
 

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