SMSC Network Card USB97C242 User Manual

USB97C242  
USB 2.0 Flash Drive  
Controller  
Datasheet  
Product Features  
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2.5 Volt, Low Power Core Operation  
3.3 Volt I/O with 5V input tolerance  
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Double Buffered Bulk Endpoint  
Bi-directional 512 Byte Buffer for Bulk Endpoint  
64 Byte RX Control Endpoint Buffer  
Complete USB Specification 2.0 Compatibility  
64 Byte TX Control Endpoint Buffer  
Includes USB 2.0 Transceiver  
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Internal or External Program Memory Interface  
A Bi-directional Control and a Bi-directional Bulk  
Endpoint are provided.  
48K Byte Internal Code Space or optional 64K Byte  
External Code Space using Flash, SRAM, or  
EPROM memory.  
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Complete System Solution for interfacing  
SmartMedia (SM), and NAND flash devices to  
USB 2.0 bus  
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On Board 12Mhz Crystal Driver Circuit  
Supports USB Bulk Only Mass Storage Compliant  
Bootable BIOS  
Internal PLL for 480Mhz USB2.0 Sampling,  
30Mhz MCU clock  
Support for the following devices:  
- SM: 2M –15MB/sec  
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Supports firmware upgrade via USB bus if sector-  
erasable Flash program memory is used  
- NAND Flash: 2M – 15MB/sec  
Built-in hardware 1-bit ECC support.  
7 GPIOs for special function use: LED indicators,  
button inputs, power control to memory devices,  
etc.  
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8051 8 bit microprocessor  
Provides low speed control functions  
Inputs capable of generating interrupts with either  
edge sensitivity  
30 Mhz execution speed at 4 cycles per instruction  
average  
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100 Pin TQFP (12x12x1.4 body) Lead-Free  
RoHS Compliant Package also available  
12K Bytes of internal SRAM for general purpose  
scratchpad  
768 Bytes of internal SRAM for general purpose  
scratchpad or program execution with external flash  
ORDERING INFORMATION  
Order Number(s):  
USB97C242-MN-xx for 100 pin TQFP package  
USB97C242-MV-04 for 100 pin TQFP Lead-Free RoHS Compliant Package  
SMSC USB97C242  
Page 1  
Revision 1.4 (05-03-07)  
DATASHEET  
 
USB 2.0 Flash Drive Controller  
Datasheet  
USB97C242 Revision History  
PAGE(S)  
SECTION/FIGURE/ENTRY  
CORRECTION  
DATE REVISED  
Rev. 1.4  
1
Cover  
Added lead-free ordering information  
02-16-06  
5
Chapter 1 – General Description  
First bullet modified under the  
following section:  
Rev. 1.3  
07-08-04  
Internal program code provides the  
following features:  
ƒ
Support for 1 to 8, 128Mb through  
2Gb, 512byte and 2048 byte page  
size, 8bit parallel NAND flash  
memories, including multiple  
memory aggregates in multi-chip-  
modules (MCM) up to 8, 2Gb  
devices (ie 16Gb), as long as  
individual memory device Chip  
Enables are pinned out in the  
MCM.  
16  
5
Table 7.1 - DC Electrical Characteristics  
Chapter 1 - General Description  
Updated High Input Leakage units.  
Rev. 1.2  
11-05-03  
Rev. 1.1  
04-03-03  
Revised list of object code software  
and licenses; internal program code  
features  
8
Chapter 3 - Pin TablesTable 3.1 –  
USB97C242 100 Pin Package  
Updated tables  
Rev. 1.1  
04-03-03  
Rev. 1.1  
04-03-03  
Rev. 1.1  
04-03-03  
Rev. 1.1  
04-03-03  
Rev. 1.1  
04-03-03  
10  
12  
22  
23  
Figure 4.1 – 100 Pin TQFP  
Diagram updated, new pin names  
Updated misc pin section  
Updated table  
Table 6.1 – USB97C242 Pin  
Descriptions  
Table 11.1 - GPIO Usage  
Chapter 12 - Typical Application  
Typical application diagram deleted  
SMSC USB97C242  
Page 3  
Revision 1.4 (05-03-07)  
DATASHEET  
 
USB 2.0 Flash Drive Controller  
Datasheet  
TABLE OF CONTENTS  
REVISION HISTORY .....................................................................................................................................................2  
CHAPTER 1 GENERAL DESCRIPTION ...................................................................................................................5  
CHAPTER 2 ACRONYMS & DEFINITION ................................................................................................................7  
2.1  
CHAPTER 3 PIN TABLES.........................................................................................................................................8  
3.1 100 Pin List......................................................................................................................................................8  
Acronyms.........................................................................................................................................................7  
CHAPTER 4 PIN CONFIGURATION.......................................................................................................................10  
CHAPTER 5 BLOCK DIAGRAM .............................................................................................................................11  
CHAPTER 6 PIN DESCRIPTIONS ..........................................................................................................................12  
6.1  
CHAPTER 7 DC PARAMETERS.............................................................................................................................16  
7.1 Maximum Guaranteed Ratings ......................................................................................................................16  
Buffer Type Descriptions................................................................................................................................15  
7.1.1 Capacitance TA = 25°C; FC = 1MHz; VDD, VDDP = 2.5V .....................................................................18  
CHAPTER 8 AC SPECIFICATIONS........................................................................................................................19  
CHAPTER 9 PACKAGE OUTLINE..........................................................................................................................20  
CHAPTER 10  
CHAPTER 11  
CHAPTER 12  
REFERENCE ..................................................................................................................................21  
GPIO USAGE TABLE.....................................................................................................................22  
TYPICAL APPLICATION ................................................................................................................23  
LIST OF FIGURES  
Figure 4.1 – 100 Pin TQFP ..........................................................................................................................................10  
Figure 9.1 – 100 Pin TQFP Package Outline, 12x12x1.4 Body (Rev A).......................................................................20  
LIST OF TABLES  
Table 3.1 – USB97C242 100 Pin Package ....................................................................................................................8  
Table 3.2 – 100 Pin TQFP .............................................................................................................................................8  
Table 6.1 – USB97C242 Pin Descriptions....................................................................................................................12  
Table 6.2 - USB97C242 Buffer Type Descriptions .......................................................................................................15  
Table 7.1 - DC Electrical Characteristics.......................................................................................................................16  
Table 9.1 – 100 Pin TQFP Package Parameters (Rev A)............................................................................................20  
Table 11.1 - GPIO Usage.............................................................................................................................................22  
SMSC USB97C242  
Page 4  
Revision 1.4 (05-03-07)  
DATASHEET  
 
USB 2.0 Flash Drive Controller  
Datasheet  
Chapter 1 General Description  
The USB97C242 is a USB2.0 Bulk Only Mass Storage Class Peripheral Controller intended for supporting  
SmartMedia (SM), and NAND flash memory devices. It provides a single chip USB reader solution for the  
SM and NAND flash devices in the market*.  
The device consists of a USB 2.0 PHY and SIE, buffers, Fast 8051 microprocessor with expanded  
scratchpad, and program SRAM, 48KB program ROM and SM controller.  
Provisions for optional external Flash Memory up to 64K bytes for program storage is provided.  
12K bytes of scratchpad SRAM and 768Bytes of scratchpad SRAM are also provided.  
Seven GPIO pins are for the 100-pin device. Provisions are made to allow dynamic attach and re-attach to  
the USB bus to allow hot swap of flash media to be implemented.  
SMSC provides the following object code software and licenses free of charge with purchase of the  
USB97C242**:  
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Windows 98 Mass Storage Class driver.  
Windows application for programming VID/PID/OEM strings, and unique serial number into serial  
EEPROM (SM reader) or NAND Flash via USB.  
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Production test and format utilities  
Password protection API and example applet.  
Firmware with field upgrade capability via USB (requires external specific model 128KB Flash for  
firmware storage).  
The Internal program code provides the following features:  
ƒ
Support for 1 to 8, 128Mb through 2Gb, 512byte and 2048 byte page size, 8bit parallel NAND flash  
memories, including multiple memory aggregates in multi-chip-modules (MCM) up to 8, 2Gb devices  
(ie 16Gb), as long as individual memory device Chip Enables are pinned out in the MCM.  
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Autodetection of NAND Flash memory type and capacity  
Supports write protect switch  
Wear leveling  
Internal VID/PID/Serial Number/OEM String storage in NAND flash itself, eliminating need for external  
serial EEPROM  
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High performance transfers (interleaving, copy block caching, etc.)  
Drive password protection  
SMSC may make complete internal specifications available for those customers requiring programming  
information, subject to SMSC’s applicable Proprietary Information Agreement (nondisclosure agreement).  
Contact your SMSC sales representative for more information.**  
SMSC USB97C242  
Page 5  
Revision 1.4 (05-03-07)  
DATASHEET  
 
USB 2.0 Flash Drive Controller  
Datasheet  
Note:  
* In order to develop, make, use, or sell readers and/or other products using or incorporating any of the  
SMSC devices made the subject of this document or to use related SMSC software programs, technical  
information and licenses under patent and other intellectual property rights from or through various persons  
or entities, including without limitation media standard companies, forums, and associations, and other  
patent holders may be required. These media standard companies, forums, and associations include  
without limitation the following: Sony Corporation (Memory Stick), SD3 LLC (Secure  
Digital/MultiMediaCard), the SSFDC Forum (SmartMedia), and the Compact Flash Association (Compact  
Flash). SMSC does not make such licenses or technical information available; does not promise or  
represent that any such licenses or technical information will actually be obtainable from or through the  
various persons or entities (including the media standard companies, forums, and associations), or with  
respect to the terms under which they may be made available; and is not responsible for the accuracy or  
sufficiency of, or otherwise with respect to, any such technical information.  
SMSC's obligations (if any) under the Terms of Sale Agreement, or any other agreement with any  
customer, or otherwise, with respect to infringement, including without limitation any obligations to defend  
or settle claims, to reimburse for costs, or to pay damages, shall not apply to any of the devices made the  
subject of this document or any software programs related to any of such devices, or to any combinations  
involving any of them, with respect to infringement or claimed infringement of any existing or future patents  
related to solid state disk or other flash memory technology or applications (“Solid State Disk Patents”). By  
making any purchase of any of the devices made the subject of this document, the customer represents,  
warrants, and agrees that it has obtained all necessary licenses under then-existing Solid State Disk  
Patents for the manufacture, use and sale of solid state disk and other flash memory products and that the  
customer will timely obtain at no cost or expense to SMSC all necessary licenses under Solid State Disk  
Patents; that the manufacture and testing by or for SMSC of the units of any of the devices made the  
subject of this document which may be sold to the customer, and any sale by SMSC of such units to the  
customer, are valid exercises of the customer’s rights and licenses under such Solid State Disk Patents;  
that SMSC shall have no obligation for royalties or otherwise under any Solid State Disk Patents by reason  
of any such manufacture, use, or sale of such units; and that SMSC shall have no obligation for any costs  
or expenses related to the customer’s obtaining or having obtained rights or licenses under any Solid State  
Disk Patents.  
SMSC MAKES NO WARRANTIES, EXPRESS, IMPLIED, OR STATUTORY, IN REGARD TO  
INFRINGEMENT OR OTHER VIOLATION OF INTELLECTUAL PROPERTY RIGHTS.  
SMSC  
DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES AGAINST INFRINGEMENT AND THE LIKE.  
No license is granted by SMSC expressly, by implication, by estoppel or otherwise, under any patent,  
trademark, copyright, mask work right, trade secret, or other intellectual property right.  
**To obtain this software program the appropriate SMSC Software License Agreement must be executed  
and in effect. Forms of these Software License Agreements may be obtained by contacting SMSC.  
SMSC USB97C242  
Page 6  
Revision 1.4 (05-03-07)  
DATASHEET  
 
USB 2.0 Flash Drive Controller  
Datasheet  
Chapter 2 Acronyms & Definition  
2.1  
Acronyms  
SM: SmartMedia  
SMC: SmartMedia Controller  
FM: Flash Media  
FMC: Flash Media Controller  
ECC: Error Checking and Correcting  
CRC: Cyclic Redundancy Checking  
SMSC USB97C242  
Page 7  
Revision 1.4 (05-03-07)  
DATASHEET  
 
USB 2.0 Flash Drive Controller  
Datasheet  
Chapter 3 Pin Tables  
Table 3.1 – USB97C242 100 Pin Package  
NAND FLASH/SMARTMEDIA INTERFACE (17 PINS)  
D0  
D4  
D1  
D5  
D2  
D6  
D3  
D7  
ALE  
nWP  
nWPS  
CLE  
nB/R  
nRE  
nCE  
nWE  
nCD  
USB INTERFACE (7 PINS)  
USB+  
USB-  
FS+  
LOOPFLTR  
FS-  
RBIAS  
RTERM  
MEMORY/IO INTERFACE (29 PINS)  
MA0  
MA4  
MA1  
MA5  
MA2  
MA6  
MA3  
MA7  
MA8  
MA9  
MA10  
MA14  
MD2  
MA11  
MA15  
MD3  
MD7  
MA12  
MD0  
MA13  
MD1  
MD4  
MD5  
MD6  
nMRD  
nIOW  
nMWR  
nIOR  
nMCE  
MISC (21 PINS)  
ROMEN  
GPIO4  
GPIO1  
GPIO5  
XTAL2  
nCS5  
GPIO20  
GPIO6  
nRESET  
nCS6  
GPIO3  
GPIO7  
XTAL1/CLKIN  
nCS4  
nCS7  
nCS3  
nCS0  
nCS1  
nCS2  
nTEST0  
nTEST1  
POWER, GROUNDS, AND NC (26 PINS)  
TOTAL 100  
3.1  
100 Pin List  
Table 3.2 – 100 Pin TQFP  
PIN #  
NAME  
MA0  
MA PIN #  
NAME  
MD5  
MA PIN #  
NAME  
51 nWE  
52 nWP  
MA PIN #  
NAME  
RBIAS  
VDDA  
FS+  
MA  
1
2
3
4
5
6
7
8
8
8
8
8
8
8
8
8
26  
27  
28  
29  
30  
31  
32  
33  
8
8
8
8
8
8
8
8
12  
12  
8
76  
77  
78  
79  
80  
81  
82  
83  
MA1  
MA2  
MA3  
MA4  
MA5  
MA6  
MA7  
MD6  
MD7  
53 nCE  
nMRD  
nMWR  
VSSIO  
nMCE  
nIOW  
54 nWPS  
55 nB/R  
USB+  
USB-  
56 nCD  
FS-  
57 nCS0  
58 VDDCORE  
RTERM  
VSSA  
SMSC USB97C242  
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Revision 1.4 (05-03-07)  
DATASHEET  
 
USB 2.0 Flash Drive Controller  
Datasheet  
PIN #  
NAME  
MA8  
MA PIN #  
NAME  
MA PIN #  
NAME  
MA PIN #  
NAME  
MA  
9
8
34  
nIOR  
8
59 nCS1  
84  
XTAL1/CL  
KIN  
10  
11  
12  
MA9  
8
8
35  
36  
37  
ROMEN  
D0  
60 VSSCORE  
61 nCS2  
85  
86  
87  
XTAL2  
MA10  
12  
VSSP  
VDDCOR  
E
D1  
62 VDDIO  
LOOPFLT  
R
12  
12  
13  
14  
MA11  
8
38  
39  
D2  
63 nCS3  
64 nCS4  
88  
89  
VDDP  
VSSCOR  
E
VDDCOR  
E
GPIO1  
8
15  
16  
VSSIO  
40  
41  
D3  
12  
12  
65 VSSIO  
90  
91  
GPIO2  
GPIO3  
8
8
MA12  
8
VSSCOR  
E
66 nCS5  
17  
18  
19  
20  
21  
22  
23  
24  
25  
MA13  
MA14  
MA15  
VDDIO  
MD0  
8
8
8
42  
43  
44  
45  
46  
47  
48  
49  
50  
D4  
67 nCS6  
68 nCS7  
69 NC  
70 NC  
71 NC  
72 NC  
73 NC  
74 NC  
75 NC  
92  
93  
94  
95  
96  
97  
98  
99  
100  
GPIO4  
GPIO5  
GPIO6  
GPIO7  
nRESET  
VSSIO  
nTEST0  
VDDIO  
nTEST1  
8
8
8
8
VDDIO  
D5  
12  
12  
12  
12  
D6  
8
8
8
8
8
D7  
MD1  
ALE  
VSSIO  
nRE  
CLE  
MD2  
MD3  
24  
12  
MD4  
SMSC USB97C242  
Page 9  
Revision 1.4 (05-03-07)  
DATASHEET  
 
USB 2.0 Flash Drive Controller  
Datasheet  
Chapter 4 Pin Configuration  
75  
51  
CLE  
nRE  
VSSIO  
ALE  
D7  
D6  
D5  
VDDIO  
D4  
VSSCORE  
D3  
VDDCORE  
D2  
RBIAS  
VDDA  
FS+  
USB+  
USB-  
FS-  
RTERM  
VSSA  
XTAL1/CLKIN  
XTAL2  
VSSP  
LOOPFLTR  
USB97C242  
VDDP  
D1  
D0  
GPIO1  
GPIO2  
GPIO3  
GPIO4  
GPIO5  
GPIO6  
GPIO7  
nRESET  
VSSIO  
nTEST0  
VDDIO  
ROMEN  
nIOR  
nIOW  
nMCE  
VSSIO  
nMWR  
nMRD  
MD7  
MD6  
MD5  
nTEST1  
1
25  
Figure 4.1 – 100 Pin TQFP  
SMSC USB97C242  
Page 10  
Revision 1.4 (05-03-07)  
DATASHEET  
 
USB 2.0 Flash Drive Controller  
Datasheet  
Chapter 5 Block Diagram  
Auto address generators  
512 Bytes EP2 TX/RX Buffer B  
512 Bytes EP2 TX/RX Buffer A  
1.25KB  
SRAM  
Address  
Address  
64 Bytes EP1RX  
64 Bytes EP1TX  
64 Bytes EP0RX  
64 Bytes EP0TX  
EP0TX_BC  
Flash Media  
Controller (FMC)  
Memory  
Cards  
Address  
Address  
EP0RX_BC  
EP1TX_BC  
32 Bit  
60MHz  
SM/  
NAND Flash  
CS[7:0]  
EP1RX_BC  
Address  
Address  
Latch phase  
8051  
3
Latch phase  
FMC  
1
Latch phase 0, 2  
SIE  
DATA  
RAMW R_A/B  
NAND Flash  
NAND Flash  
SM  
ECC  
Flash  
Media  
DMA  
Unit  
Controller  
Control/  
Status  
Control/  
Status  
RAMRD_A/B  
Address  
Data  
@
15Mhz  
32 bit  
NAND Flash  
NAND Flash  
NAND Flash  
NAND Flash  
Clocked byPhase 0, 2 Clock  
NAND Flash  
SIE  
12K Byte  
Scratchpad  
SRAM  
32 bit 15MHz Data Buss  
( Serial Interface Engine  
)
SIE Control Regs  
USB 2.0 PHY  
( Transciever )  
GPIO  
7
pins  
Configuration and Control  
Scratchpad  
SRAM (768 Byte)  
Clock Generation  
Osc  
48KB ROM  
ROMEN  
Interrupt Controller  
Program Memory/ IO  
Bus  
MEM/IO Bus  
29pins  
FAST 8051  
CPU CORE  
CLOCKOUT  
12 MHz  
Clocked by Phase  
3
Clock  
SMSC USB97C242  
Page 11  
Revision 1.4 (05-03-07)  
DATASHEET  
 
USB 2.0 Flash Drive Controller  
Datasheet  
Chapter 6 Pin Descriptions  
This section provides a detailed description of each signal. The signals are arranged in functional groups  
according to their associated interface.  
The “n” symbol in the signal name indicates that the active, or asserted state occurs when the signal is at a  
low voltage level. When “n” is not present before the signal name, the signal is asserted when at the high  
voltage level.  
The terms assertion and negation are used exclusively. This is done to avoid confusion when working with  
a mixture of “active low” and “active high” signal. The term assert, or assertion indicates that a signal is  
active, independent of whether that level is represented by a high or low voltage. The term negate, or  
negation indicates that a signal is inactive.  
Table 6.1 – USB97C242 Pin Descriptions  
BUFFER  
TYPE  
NAME  
SYMBOL  
DESCRIPTION  
NAND FLASH/SMARTMEDIA INTERFACE  
SM  
nWP  
O12  
O12  
O12  
This pin is an active low write protect signal for the SM or NAND flash  
device.  
Write  
Protect  
SM  
ALE  
CLE  
This pin is an active high Address Latch Enable signal for the SM or  
NAND flash device.  
Address  
Strobe  
SM  
This pin is an active high Command Latch Enable signal for the SM or  
NAND flash device.  
Command  
Strobe  
SM  
D[7:0]  
I/OPU12 These pins are the bi-directional data signal D7-D0.  
Data7-0  
The bi-directional input signal should have an internal weak pull-up  
resister on the input.  
SM  
nRE  
nWE  
O24  
O12  
IPU  
This pin is an active low read strobe signal for SM or NAND flash device.  
Read  
Enable  
SM  
This pin is an active low write strobe signal for SM or NAND flash device.  
Write  
Enable  
SM  
nWPS  
A write-protect seal is detected, when this pin is low.  
This pin has an internal weak pull-up resistor.  
Write  
Protect  
Switch  
SM  
nB/R  
nCE  
IPU  
This pin is connected to the BSY/RDY pin of the SM or NAND flash  
device.  
Busy or  
Data Ready  
This pin has an internal weak pull-up resistor.  
SM  
OPU8 This pin is the active low chip enable signal to the SM or NAND flash  
device.  
Chip  
Enable  
This pin should be used to support a single SM or NAND flash device  
only.  
SMSC USB97C242  
Page 12  
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DATASHEET  
 
USB 2.0 Flash Drive Controller  
Datasheet  
BUFFER  
TYPE  
NAME  
SYMBOL  
DESCRIPTION  
SM  
nCD  
IPU  
This is the card detection signal from SM device to indicate if the device  
is inserted.  
Card  
Detection  
This pin has internal weak pull-up resistor.  
USB INTERFACE  
USB Bus  
Data  
USB-  
USB+  
I/O-U  
These pins connect to the USB bus data signals.  
USB  
Transceiver  
Filter  
LOOPFLTR  
This pin provides the ability to supplement the internal filtering of the  
transceiver with an external network, if required.  
USB  
Transceiver  
Bias  
RBIAS  
A precision 9.09K resistor is attached from ground to this pin to set the  
transceiver’s internal bias currents.  
Termination  
Resistor  
RTERM  
A precision 1.5K resistor is attached to this pin from a 3.3V supply.  
Full Speed  
USB Data  
FS-  
I/O-U  
These pins connect to the USB- and USB+ pins through 31.6 ohm series  
resistors.  
FS+  
MEMORY/IO INTERFACE  
Memory  
Data Bus  
MD[7:0]  
I/OPU8 When ROMEN = 0, these signals are used to transfer data between the  
internal CPU and the external program memory.  
When ROMEN = 1, internal weak pull up are activated to prevent these  
pins from floating.  
Memory  
Address  
Bus  
MA[15:0]  
nMWR  
nMRD  
O8  
O8  
O8  
O8  
These signals address memory locations within the external memory.  
Memory  
Read  
Strobe  
Program Memory Write; active low  
Memory  
Read  
Strobe  
Program Memory Read; active low  
Memory  
Chip  
nMCE  
Program Memory Chip Enable; active low.  
Enable  
This signal shall be de-asserted, when all of the following conditions are  
met:  
IDLE bit (PCON.0) is 1.  
INT2 is negated  
SLEEP bit of CLOCK_SEL is 1.  
This signal shall be asserted whenever any of the three conditions are  
no longer met.  
I/O Read  
Strobe  
nIOR  
O8  
O8  
This is a active low I/O Read strobe signal of Xdata bus.  
This is a active low I/O Write strobe signal of Xdata bus.  
I/O Write  
Strobe  
nIOW.  
SMSC USB97C242  
Page 13  
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DATASHEET  
 
USB 2.0 Flash Drive Controller  
Datasheet  
BUFFER  
TYPE  
NAME  
SYMBOL  
DESCRIPTION  
MISC  
ICLKx 12Mhz Crystal or external clock input.  
Crystal  
Input/Extern  
al Clock  
Input  
XTAL1/  
CLKIN  
This pin can be connected to one terminal of the crystal or can be  
connected to an external 12Mhz clock when a crystal is not used.  
Crystal  
Output  
XTAL2  
OCLKx 12Mhz Crystal  
This is the other terminal of the crystal, or left open when an external  
clock source is used to drive XTAL1/CLKIN. It may not be used to drive  
any external circuitry other than the crystal circuit.  
Internal  
ROMEN  
ROMEN  
IPU  
When tied low, an external program memory should be connected to the  
memory/data bus. The USB97C242 uses this external bus for program  
execution.  
When this pin is left unconnected or tied high, the USB97C242 uses the  
internal ROM for program execution.  
The state of this pin is latched internally on the rising edge of nRESET to  
determine if internal or external program memory is used.  
The state latched is stored in ROMEN bit of GPIO_IN1 register.  
General  
Purpose I/O  
GPIO1  
GPIO2  
GPIO3  
I/O8  
This pin may be used either as input, edge sensitive interrupt input, or  
output. See Chapter 11 for usage by program in internal ROM.  
General  
Purpose I/O  
I/OPU8 This pin may be used either as input, edge sensitive interrupt input, or  
output. See Chapter 11 for usage by program in internal ROM.  
General  
Purpose I/O  
I/O8  
I/O8  
This pin may be used either as input, edge sensitive interrupt input, or  
output. See Chapter 11 for usage by program in internal ROM.  
General  
Purpose I/O  
GPIO[7:4]  
nCS[7:0]  
These pins may be used either as input, edge sensitive interrupt input, or  
output. See Chapter 11 for usage by program in internal ROM.  
NAND flash  
Chip Select  
Signal  
OPU8 These pins can be used to chip enable the NAND flash devices, when  
multiple NAND flash devices are used.  
RESET  
input  
nRESET  
IS  
I
This active low signal is used by the system to reset the chip. The active  
low pulse should be at least 100ns wide.  
TEST Input nTEST[0:1]  
These signals are used for testing the chip. User should normally leave  
them unconnected.  
POWER, GROUNDS, AND NO CONNECTS  
+2.5V Core power  
VDD  
VDDIO  
VDDP  
VSSP  
VDDA  
VSSA  
GND  
+3.3V I/O power  
+2.5 Analog power  
Analog Ground Reference  
+3.3V Analog power  
Analog Ground Reference  
Ground Reference  
SMSC USB97C242  
Page 14  
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DATASHEET  
 
USB 2.0 Flash Drive Controller  
Datasheet  
Note: nMCE is normally asserted except when the 8051 is in standby mode.  
6.1  
Buffer Type Descriptions  
Table 6.2 - USB97C242 Buffer Type Descriptions  
BUFFER  
DESCRIPTION  
I
Input  
IPU  
IPD  
Input with internal weak pull-up resistor.  
Input with internal weak pull-down  
resistor.  
IS  
Input with Schmitt trigger  
I/O4  
Input/Output with 4mA drive  
I/OD4  
I/O8  
Input/Open drain output … 4mA sink  
Input/Output with 8mA drive  
I/OD8  
I/OPD8  
Input/Open drain output … 8mA sink  
Input/Output with 8mA drive and  
controlled weak pull down.  
I/OPU8  
Input/Output with 8mA drive and  
controlled weak pull up.  
O4  
O8  
Output with 4mA drive  
Output with 8mA drive  
OPD8  
Output with 8mA drive and controlled  
weak pull down.  
OPU8  
Output with 8mA drive and controlled  
weak pull up.  
I/O12  
Output with 12mA drive  
I/OPU12  
Input/Output with 12mA drive and  
controlled weak pull up on input.  
OPU12  
OPD12  
Output with 12mA drive and controlled  
weak pull up.  
Output with 12mA drive and controlled  
weak pull down.  
O12  
OD12  
ICLKx  
OCLKx  
I/O-U  
Output with 12mA drive  
Open drain….12mA sink  
XTAL clock input  
XTAL clock output  
Defined in USB specification  
SMSC USB97C242  
Page 15  
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USB 2.0 Flash Drive Controller  
Datasheet  
Chapter 7 DC Parameters  
7.1  
Maximum Guaranteed Ratings  
Operating Temperature Range........................................................................................................................... 0oC to +70oC  
Storage Temperature Range............................................................................................................................-55o to +150oC  
Lead Temperature Range (soldering, 10 seconds)..................................................................................................... +325oC  
Positive Voltage on any pin, with respect to Ground ........................................................................................................5.5V  
Negative Voltage on any pin, with respect to Ground......................................................................................................-0.3V  
Maximum VDD, VDDP ........................................................................................................................................................+3.0V  
Maximum VDDIO, VDDA ......................................................................................................................................................+4.0V  
*Stresses above the specified parameters could cause permanent damage to the device. This is a stress rating only and  
functional operation of the device at any other condition above those indicated in the operation sections of this  
specification is not implied.  
Note:  
When powering this device from laboratory or system power supplies, it is important that the Absolute  
Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage  
spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC  
power line may appear on the DC output. When this possibility exists, it is suggested that a clamp circuit  
be used.  
Table 7.1 - DC Electrical Characteristics  
(TA = 0°C - 70°C, VDDIO, VDDA= +3.3 V ± 10%, VDD, VDDP = +2.5 V ± 10%,)  
PARAMETER  
SYMBOL  
MIN  
2.0  
TYP  
MAX  
UNITS  
COMMENTS  
I Type Input Buffer  
VILI  
VIHI  
0.8  
V
V
TTL Levels  
Low Input Level  
High Input Level  
ICLK Input Buffer  
VILCK  
VIHCK  
0.4  
V
V
Low Input Level  
2.2  
High Input Level  
Input Leakage  
(All I and IS buffers)  
IIL  
-10  
-10  
+10  
+10  
uA  
uA  
V
IN = 0  
Low Input Leakage  
High Input Leakage  
IIH  
VIN = VDDIO  
SMSC USB97C242  
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Datasheet  
PARAMETER  
SYMBOL  
MIN  
TYP  
MAX  
UNITS  
COMMENTS  
O8 Type Buffer  
VOL  
0.4  
V
IOL = 8 mA @ VDDIO  
Low Output Level  
= 3.3V  
I
OH = -4mA @ VDDIO  
VOH  
2.4  
-10  
V
High Output Level  
Output Leakage  
= 3.3V  
IOL  
+10  
0.4  
uA  
V
IN = 0 to VDDIO  
(Note 7.1)  
I/O8 Type Buffer  
Low Output Level  
VOL  
VOH  
IOL  
V
V
IOL = 8 mA @ VDDIO  
= 3.3V  
IOH = -4 mA @ VDDIO  
2.4  
-10  
High Output Level  
= 3.3V  
+10  
0.4  
µA  
Output Leakage  
V
IN = 0 to VDDIO  
(Note 7.1)  
I/O12 Type Buffer  
Low Output Level  
VOL  
V
V
IOL = 12 mA @  
V
DDIOE = 3.3V  
IOH = -6mA @ VDDIO  
= 3.3V  
High Output Level  
VOH  
2.4  
-10  
V
IN = 0 to VDDIO  
Output Leakage  
IOL  
+10  
0.4  
µA  
V
(Note 7.1,Note 7.3)  
I/O24 Type Buffer  
Low Output Level  
High Output Level  
Output Leakage  
VOL  
IOL = 24 mA @ VDDIO  
= 3.3V  
IOH = -12 mA @  
VOH  
2.4  
V
V
DDIO = 3.3V  
VIN = 0 to VDDIO  
IOL  
-10  
+10  
µA  
(Note 7.1,Note 7.3)  
SMSC USB97C242  
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Datasheet  
PARAMETER  
SYMBOL  
MIN  
TYP  
MAX  
UNITS  
COMMENTS  
IO-U  
Note 7.2  
Supply Current Unconfigured  
ICCINIT  
85  
60  
mA  
mA  
@ VDD, VDDP = 2.5V  
@ VDDIO, VDDA  
3.3V  
=
Supply Current Active  
Supply Current Standby  
ICC  
85  
60  
110  
70  
mA  
mA  
@ VDD, VDDP = 2.5V  
@ VDDIO, VDDA  
3.3V  
=
ICSBY  
150  
150  
@ VDD, VDDP = 2.5V  
µA  
@ VDDIO, VDDA  
3.3V  
=
Note 7.1 Output leakage is measured with the current pins in high impedance.  
Note 7.2 See Appendix A for USB DC electrical characteristics.  
Note 7.3 Output leakage is valid only on pins without internal weak pull ups or pull downs.  
7.1.1 Capacitance TA = 25°C; FC = 1MHz; VDD, VDDP = 2.5V  
LIMITS  
PARAMETER  
Clock Input Capacitance  
Input Capacitance  
SYMBOL MIN TYP MAX UNIT  
TEST CONDITION  
CIN  
CIN  
20  
10  
20  
pF  
pF  
pF  
All pins except USB pins  
(and pins under test tied  
to AC ground)  
Output Capacitance  
COUT  
SMSC USB97C242  
Page 18  
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USB 2.0 Flash Drive Controller  
Datasheet  
Chapter 8 AC Specifications  
Refer to the appropriate specification document in the chapter of “Reference” for each flash media device or USB  
interface.  
SMSC USB97C242  
Page 19  
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Datasheet  
Chapter 9 Package Outline  
Figure 9.1 – 100 Pin TQFP Package Outline, 12x12x1.4 Body (Rev A)  
Table 9.1 – 100 Pin TQFP Package Parameters (Rev A)  
MIN  
~
NOMINAL  
MAX  
1.60  
0.15  
1.45  
14.20  
12.20  
14.20  
12.20  
0.20  
0.75  
~
REMARKS  
Overall Package Height  
Standoff  
~
~
~
~
~
~
~
~
A
A1  
A2  
D
D1  
E
E1  
H
L
0.05  
1.35  
13.80  
11.80  
13.80  
11.80  
0.09  
0.45  
~
Body Thickness  
X Span  
X body Size  
Y Span  
Y body Size  
Lead Frame Thickness  
Lead Foot Length  
Lead Length  
0.60  
1.00  
0.40 Basic  
L1  
e
Lead Pitch  
Lead Foot Angle  
Lead Width  
0o  
0.13  
0.08  
0.08  
~
~
0.16  
~
~
~
7o  
0.23  
~
0.20  
0.08  
θ
W
R1  
R2  
ccc  
Lead Shoulder Radius  
Lead Foot Radius  
Coplanarity  
Notes:  
1 Controlling Unit: millimeter.  
2 Tolerance on the position of the leads is ± 0.035 mm maximum.  
3 Package body dimensions D1 and E1 do not include the mold protrusion.  
Maximum mold protrusion is 0.25 mm.  
4 Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane.  
5 Details of pin 1 identifier are optional but must be located within the zone indicated.  
SMSC USB97C242  
Page 20  
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DATASHEET  
 
USB 2.0 Flash Drive Controller  
Datasheet  
Chapter 10 Reference  
1. SmartMediaTM Electrical Specification Version 1.30  
2. SmartMediaTM Physical Format Specifications Version 1.30  
3. SmartMediaTM Logical Format Specifications Version 1.20  
4. SMIL (SmartMedia Interface Library) Software Edition Version 1.00, Toshiba Corporation, 01, July, 2000  
5. SMIL (SmartMedia Interface Library) Hardware Edition Version 1.00, Toshiba Corporation, 01, July, 2000  
6. K9K2G08U0M, 256Mx8 Bit NAND Flash Memory Data Sheet, Samsung.  
7. Universal Serial Bus Specification Rev 2.0  
SMSC USB97C242  
Page 21  
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DATASHEET  
 
USB 2.0 Flash Drive Controller  
Datasheet  
Chapter 11 GPIO Usage Table  
Table 11.1 - GPIO Usage  
ACTIVE  
NAME  
GPIO1  
SYMBOL  
DESCRIPTION AND NOTE  
LEVEL  
H
H
Flash Media Activity LED  
Indicates media activity. Media or  
USB cable must not be removed  
with LED lit. Active High.  
GPIO2  
Ready/Busy# 1/4  
Ready/Busy# line from NAND  
Flash chips 0, or 0 & 4  
GPIO3  
GPIO4  
H
H
V_BUS  
USB V bus dectect  
Ready/Busy# for Chips 1/5  
Ready/Busy# line from NAND  
Flash chips 1, or 1 & 5  
GPIO5  
H
HS_IND/Ready/Busy# 2/6  
In Rom -03; HS_LED output  
indicator; in later ROM patterns,  
the Ready/Busy# line from NAND  
Flash chips 2, or 2 & 6  
GPIO6  
GPIO7  
H
H
A16  
A16 address line when external  
Rom is used; unused output  
otherwise.  
Ready/Busy# 3/7  
Ready/Busy# line from NAND  
Flash chips 3, or 3 & 7  
SMSC USB97C242  
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USB 2.0 Flash Drive Controller  
Datasheet  
Chapter 12 Typical Application  
Contact SMSC Sales for the latest reference designs and information and details about software licenses and the  
latest capabilities/features included in current production versions of the internal ROM.  
SMSC USB97C242  
Page 23  
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DATASHEET  
 

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